Analysis of multicast ATM switching networks using CRWR scheme1

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Abstract

A (large) multicast ATM switch with external structure of output queueing and internal structure of buffered MINs (multistage interconnection networks) is considered in the paper, where the buffered MIN (also called switching network) is composed of switching elements with shared buffer output queueing. The cell replication while routing (CRWR) scheme is used in the switch to implement multicast function. In this paper, we study the performance of the switch with multicast traffic, mainly via computer simulations. The multicast traffic can be random and bursty. We found that compared to unicast traffic, multicast traffic with truncated geometric distribution of cell fanouts has only a slightly worse impact on the performance of switching elements in isolation or in the last stage of the switching network. The multicast traffic has no worse effect on the switch output buffer behavior and cell delay in the switching network. Moreover, using multiple MINs in parallel can substantially improve the switching network performance for highly bursty traffic. Some analytical approximations are given which could be useful in the dimensioning of switching networks.

Introduction

To support efficiently point to multipoint communications such as teleconferencing and LAN-LAN interconnection, an ATM switch requires a multicast capability which is able to establish connections between one of the switch inlets to a subset of its outlets. How to replicate cells and route the individual copies to their corresponding switch outlets are thus additional issues in the design of multicast ATM switches. Several cell replication schemes have been proposed in the literature, which can be roughly classified into three categories: (1) cell replication before routing (i.e., cascade of copy network and point-to-point switch) 1, 2, 3, (2) cell replication while routing 4, 5 and (3) cell recycling (i.e., to feed cells from switch outlets back to switch inlets to generate copies) 6, 7. It is likely that switches with various architectures will choose different cell replication schemes or a combination to implement multicast function.

Previous study reveals that for small (point-to-point) ATM switches (e.g., 8×8, 16×16 or even 32×32), shared buffer output queueing gives the best delay/throughput performance [8]. Many manufacturers have adopted this queueing strategy in their switch design 9, 10. By adding a multicast tree table, the switch with shared buffer output queueing can be readily extended to a multicast ATM switch 11, 12, which still yields the best delay/throughput performance. In such a multicast switch, cell replication is performed via table lookup (cell replication while routing scheme). To build a large ATM switch from those small switches (also called switching elements), probably the most cost-effective way is to use the multistage interconnection network (MIN) structure. It is clear that the second cell replication scheme, cell replication while routing, is very suitable for this bufferd MIN structure in providing multicast function [4]. Under this scheme, cell replication is easily and efficiently performed in each stage of MIN via table lookup, as one will see in Section 2. For unbuffered MIN architectures, they are likely to choose the first or third cell replication scheme in the design of multicast ATM switches [13].

In this paper, we will consider a multicast ATM switch with buffered MIN structure and using cell replication while routing scheme, where the buffered MIN is composed of switching elements with shared buffer output queueing. The buffered MIN is also called a switching network (SN) in the paper and we will use the terminology interchangeably. Our main goal is to study the performance of a single switch as well as the switching network under both random and bursty multicast input traffic. Due to the complexity of multicast traffic and shared buffer queueing, we mainly resort to computer simulations in our study. Based on simulation results, we develop some simple analytical approximations which are useful in the dimensioning of switching networks. Performance analysis of multistage switching networks has been conducted before, for instance in 14, 15, 16, however, only for unicast traffic. Unlike previous work, here we will concentrate on multicast traffic.

The rest of the paper is organized as follows. In Section 2, we describe the multicast ATM switch under study in more detail and illustrate how multicast cells are stored and replicated inside the switch. The multicast traffic model is given in Section 3. Performance of the multicast switch is thoroughly studied in Section 4. Finally, Section 5summarizes our findings and conclusions.

Section snippets

The multicast ATM switch

To be clear, let us start with an ATM switch with shared buffer output queueing. In the switch with shared buffer output queueing, multicast cells can be easily replicated via table lookup as depicted in Fig. 1 where an incoming multicast cell is copied to switch outlets 0, 1 and 3. Note that we only need to store the incoming multicast cell instead of all its copies in the shared buffer memory (SBM) and send the address of the multicast cell in the SBM to address queues connected to switch

Multicast traffic model

Here we consider two types of multicast input traffic: random and bursty traffic. For random input traffic, cell arrivals on each inlet of the switch are independent and identifically distributed (i.i.d.) from slot to slot. In a given slot, there is a cell arrival on a switch inlet with probability σ and no cell arrivals with probability 1−σ, where σ is the average traffic load of the switch inlet. Using the term fanout to denote the number of copies of a multicast cell to be generated by the

Switch output buffer behavior

Consider the multicast ATM switch shown in Fig. 4 where all the inlets and outlets are slotted in time. One slot is the time interval to carry exactly one cell. As cell delays inside the switch are constant, we could neglect the internal switching fabric when analyzing the switch output buffer behavior. In other words, each output buffer of the switch can be modeled as a discrete-time single-server queue where cell arrivals to the queue are determined directly from the cell arrivals to the

Concluding remarks

Some initial results are found on switch performance under multicast traffic with truncated geometric cell fanout. Compared to unicast traffic, first, for N×N switches with output queueing, multicast traffic has no worse impact on the switch performance (buffer overflow probability and cell delay). Second, for an isolated S×S SE with shared buffer output queueing, multicast traffic with small mean cell fanouts has a bit worse effect on the tail distributions of shared buffer contents, which is

Acknowledgements

The authors would like to thank the reviewers for their valuable comments and suggestions.

Yijun Xiong received the B.S. and M.S. degrees from Shanghai Jiao Tong University, China, in 1984 and 1987, respectively, and the Ph.D. degree from the University of Ghent, Belgium, in 1994, all in electrical engineering. Since 1996, he has been an assistant professor of Electrical and Computer Engineering at Louisiana State University, Baton Rouge, LA. Previously, he was with the Research Center of Alcatel Bell Telephone (Antwerp, Belgium) from August 1989 to August 1992, the Laboratory for

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    Yijun Xiong received the B.S. and M.S. degrees from Shanghai Jiao Tong University, China, in 1984 and 1987, respectively, and the Ph.D. degree from the University of Ghent, Belgium, in 1994, all in electrical engineering. Since 1996, he has been an assistant professor of Electrical and Computer Engineering at Louisiana State University, Baton Rouge, LA. Previously, he was with the Research Center of Alcatel Bell Telephone (Antwerp, Belgium) from August 1989 to August 1992, the Laboratory for Communications Engineering, University of Ghent (Belgium), from September 1992 to June 1994, and INRS-Telecommunications (Montreal, Canada) from July 1994 to September 1996. His current research interests include multicast ATM switches, network resource management, network survivability and queueing theory.

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    Lorne G. Mason, INRS-Telecommunications, University of Quebec, obtained the B.Sc. and Ph.D. degrees in mechanical engineering from the University of Saskatchewan, Canada, in 1963 and 1972, respectively. He was with Bristol Aerojet in Winnipeg, Manitoba, from 1963 to 1965 involved in the design of the Black Brant rockets. He joined the British Columbia Telephone Co. as a traffic engineer in 1966 and again in 1972 as a consultant for planning digital networks. In 1973 he served as a consultant to Yale University, where he, in collaboration with Professor K.S. Narendra, pioneered the use of learning automata for adaptive routing in telecommunication networks. Between 1974 and 1977, he was with Bell-Northern Research where he developed planning tools and methods for digital network evolution and state-dependent routing. Since 1977 he has been with INRS-Telecommunications where he currently holds the title of full professor. He also holds a position of “Professeur Associée” at ENST (Telecom Paris). His primary research interests are in the application of control theory and operations research methods to telecommunication network design and management. He has held numerous industrial research contracts and NSERC strategic grants in the area of broadband network design and analysis and has over 50 publications on the subject in leading conferences and journals. Professor Mason is a participant in the Network of Centers of Excellence program sponsored by the Canadian government, where he is project leader on broadband network control. He was co-recipient of the 1993 STENTOR Award for collaborative research in telecommunications for his contributions to state-dependent routing. He recently organized and chaired the joint IFIP/IEEE conference on Broadband Communications, and was editor of the proceedings published in book form by Chapman and Hall. He is technical co-chairman for the upcoming IEEE ATM'98 workshop. Lorne G. Mason is a CIPS member and Canadian representative to IFIP TC6 committee.

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    This work was supported under contract by General DataComm. Part of the paper was presented at IEEE INFOCOM'97 (Kobe, Japan).

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