Elsevier

Neural Networks

Volume 11, Issue 9, December 1998, Pages 1671-1684
Neural Networks

Contributed article
A fast neural-network algorithm for VLSI cell placement

https://doi.org/10.1016/S0893-6080(98)00089-6Get rights and content

Abstract

Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.

Introduction

Cell placement is an important problem arising in various VLSI circuit design styles such as standard cell, gate array and Field Programming Gate Array (FPGA). Given a circuit description, the problem is to find a layout of the circuit while minimizing some cost function. Usually two closely related criteria are used to construct a cost function: minimization of the routing length and minimization of the chip area. In some design styles (e.g. standard cell), minimization of the area is equivalent to minimization of the routing length (Shahookar and Mazumder, 1991), whereas in some others area is fixed (e.g. FPGA). If the area is fixed, minimization of the routing length is necessary for the routability of the circuit using the available routing resources. Minimization of the routing length also minimizes the propagation delays of the circuit, hence increasing its speed (Shahookar and Mazumder, 1991).

Although the cell placement problem has different characteristics related to the technology used in different design styles, key features of the problem remain the same. This enables a general definition for the cell placement problem to be made which is valid for all design styles. The problem is decomposed into two phases such that the first phase is same for all design styles and the second phase depends on the design style. An instance of the first phase of the cell placement problem consists of a hypergraph Ω(C, N) representing the circuit to be placed, and a rectangular grid of clusters with P rows and Q columns where the circuit will be placed. Hypergraph Ω(C, N) consists of a vertex set C representing the cells of the circuit, a hyperedge set N representing the nets of the circuit, a cell weight function ωcell:CN, and a net weight function ωnet:NN, where N represents the set of natural numbers. The aim is to partition the vertex set C into P×Q clusters such that the routing cost is minimized and the weights of the clusters are nearly balanced. The weight of a cluster is the sum of the weights of the cells in that cluster. In general, cell weight function is used to encode the areas of cells, and net weight function is used to increase the importance of some nets which may be crucial for the performance of the circuit. The rectangular grid of clusters is used for estimating the final locations of the cells. The computation of routing cost is discussed in detail in Section 2.

Fig. 1(a) illustrates an example circuit with 16 cells and 19 nets (Shahookar and Mazumder, 1991). The circuit has 3 input (I1, I2, I3) and 2 output (O1, O2) pads. Pads may be interpreted as cells which must be mapped to the boundaries of the cluster grid. The example circuit in Fig. 1(a) may be represented with a hypergraph Ω(C, N) according to the above definition as:

Unit cell and net weights are assumed in this example. Fig. 1(b) shows the placement of this circuit to a 4×4 grid of 16 clusters.

The second phase of the cell placement problem is the mapping of the cells in the clusters to their final locations in the layout. In standard cell design style, cells are used for constructing rows, and in gate array design style, cells are mapped to rows or grid locations according to the type of the gate array used (Sechen, 1988). Some gate arrays consist of modules forming a rectangular grid. For this type of gate arrays the second phase of the problem may be skipped by choosing the number of rows and columns of the cluster grid to be equal to the number of rows and columns of the module grid, respectively. Symmetrical FPGAs consist of logic blocks forming a rectangular grid (Rose et al., 1992, Rose et al., 1993). Hence, the second phase of the problem can be similarly skipped for symmetrical FPGAs. This two phase modeling enables the development of heuristics for the first phase of the problem which are independent of the design style.

Since cell placement problem is NP-Hard (Lengauer, 1990), finding efficient placement heuristics is an important research issue. In the last decade, neurocomputing approaches based on Hopfield model were successfully applied to various combinatorial optimization problems such as the traveling salesman problem (Peterson and Söderberg, 1989; VandenBout and Miller, 1989; Takahashi, 1997), scheduling problem (Gislén et al., 1992), mapping problem (Bultan and Aykanat, 1992), knapsack problem (Ohlsson et al., 1993; Ohlsson and Pi, 1997), communication routing problem (Hökkinen et al., 1998), graph partitioning problem (Herault and Niez, 1989; Peterson and Söderberg, 1989; VandenBout and Miller, 1990), graph layout problem (Cimikowski and Shope, 1996), circuit partitioning problem (Yih and Mazumder, 1990; Bultan and Aykanat, 1995). In this paper, the Mean Field Annealing (MFA) technique is applied to the cell placement problem. MFA is a new approach for solving combinatorial optimization problems (Peterson and Söderberg, 1989; VandenBout and Miller, 1989, VandenBout and Miller, 1990; Gislén et al., 1992; Bultan and Aykanat, 1992, Bultan and Aykanat, 1995; Ohlsson et al., 1993; Ohlsson and Pi, 1997; Hökkinen et al., 1998). MFA combines the collective computation property of Hopfield neural networks (Hopfield and Tank, 1985) with the annealing notion of Simulated Annealing (SA) (Kirkpatrick et al., 1983). In MFA, discrete variables called spins (or neurons) are used for encoding configurations of combinatorial optimization problems. An energy function written in terms of spins is used for representing the cost function of the problem. Then, using the expected values of these discrete variables, a nondeterministic gradient descent type relaxation scheme is used to find a configuration of the spins which minimizes the energy function associated with them.

In this paper, a MFA-based cell placement algorithm is proposed. In order to show the performance of the proposed algorithm on concrete examples MFA formulations are derived for symmetrical-array FPGA design style. However, the MFA formulations proposed for FPGAs are general enough so that they can easily be applied to the first phase of the cell placement problem in other design styles with minor modifications.

The organization of the paper is as follows. Section 2discusses the method used for approximating the routing cost of the placement. FPGA design style is briefly summarized in Section 3. Section 4begins with the presentation of the general guidelines for applying MFA technique to combinatorial optimization problems. Then, the proposed formulation and implementation of the MFA algorithm for the cell placement problem following these guidelines are presented. The encoding scheme used in the proposed formulation is discussed in Section 4.1. The proposed energy function formulation and derivation of the mean field theory equations are presented in Section 4.2and Section 4.3, respectively. The parameter selection and cooling schedule are discussed in Section 4.4. Finally, experimental results which evaluate the relative performance of the proposed algorithm are discussed in Section 5.

Section snippets

Routing cost

Computation of the routing cost is the crucial part of the cell placement problem. In the first phase of the problem, cells are partitioned to P×Q clusters which form a rectangular grid. Fig. 1(b) shows the partitioning of the circuit in Fig. 1(a) to a 4×4 grid. Initially, it is assumed that all clusters have the same size, forming a uniform grid as in Fig. 1(b). After the cells are mapped to the clusters, areas of the clusters may be different, resulting with a nonuniform grid. If the clusters

FPGA design style

Field Programmable Gate Arrays (FPGAs) were widely used in industry in recent years. Because they provide cheap and flexible usage, fast manufacturing turnaround time and low prototype cost, many designers prefer to use them in their applications. Several types of FPGAs were introduced over the last years, which differ from each other by their programming technologies, logic block architectures and routing network architectures (Rose et al., 1992). They can be classified into four main

Applying MFA to the cell placement problem

MFA technique merges the collective computation and the annealing properties of Hopfield neural networks (Hopfield and Tank, 1985) and SA (Kirkpatrick et al., 1983), respectively, to obtain a general algorithm for solving combinatorial optimization problems. A combinatorial optimization problem consists of a set of configurations and a cost function. For example, for the cell placement problem the set of configurations corresponds to the set of all possible placements of the input circuit.

Experimental results

This section presents experimental performance evaluation of the proposed MFA algorithm in comparison with Xilinx Automated Placement and Routing (APR 3.30) program which uses simulated annealing algorithm in placement. Our MFA algorithm was implemented in C language and run on Sun-4 ELC workstations. Seven MCNC benchmark circuits were used to test the performance and efficiency of both programs. Xilinx 3000 series chips were used as the target FPGAs. The circuits were mapped into 3000 series

Conclusions

In this paper, a fast nondeterministic cell placement algorithm was proposed for VLSI design automation based on Mean Field Annealing (MFA). The performance of the proposed placement algorithm was evaluated in comparison with the commercial automated circuit design software Xilinx Automatic Place and Route (APR) tool for the placement of seven MCNC benchmark circuits. The results show that neurocomputing approaches such as the MFA technique can be applied to practical problems and can compete

Acknowledgements

This work is partially supported by the Commission of the European Communities, Directorate General for Industry under contract ITDC 204-82166, and the Turkish Science and Research Council under grant EEEAG-160. The authors would like to thank Jonathan Rose for helpful discussions on FPGAs.

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