PARCIS: a robust parallel VLSI circuit simulator

Abstract

The accurate verification of VLSI circuits is essential for their successful and economic production but is an extremely time consuming process for the large circuits of today. This paper describes a robust parallel circuit simulator, PARCIS, designed for a message passing multiprocessing system. It uses a demand driven technique, based on the analysis of hierarchically partitioned circuits. The computation time is reduced by decoupling the circuit equations and distributing the computational load over many processors. On each processor, the circuit blocks, compacted in hierarchical levels, are analyzed asynchronously according to their temporal activity. Currently the PARCIS system is running on a network of transputers. To demonstrate the effectiveness of the proposed simulation program, results are presented for the simulation of typical digital circuits, showing that the execution time decreases in a constant rate as the number of processors (transputers) increases.

Introduction

As the integrated circuit fabrication technology advances, the complexity of VLSI circuits increases. The accurate verification of such circuits is essential for their successful and economic production but is an extremely time consuming procedure.

In the past, a number of simulators have been developed for this purpose. Logic simulators, with their fast responses, are valuable for debugging the higher levels of a design. Still, there are many cases where the information delivered by a circuit level – transient – simulator is indispensable. For example, only transient simulators can predict with accuracy the time domain responses of signals in: (a) critical paths within VLSIs required to meet today's demands for high clock rates, (b) fast bipolar chips used for the manufacture of high speed computers, and (c) modern mixed analog–digital circuits. However, simulation methods as used in SPICE [14]are limited in the size of circuits that can be simulated because of the large computation time they require.

To overcome the problem of computation time a series of improvements have been added to circuit simulators. It is recognized that the elements of practical circuits are not fully interconnected [9]and this led, in the past, to the development of Sparse Matrix Techniques 3, 7with superlinear time complexity and further into Block Diagonal Matrix Techniques [16]. Techniques for speeding up the convergence of the nonlinear circuit equations have been proposed [15]as well as techniques supporting a hierarchical approach to the analysis of the circuit 12, 13, 5, 2, 19.

Latency exploitation, e.g. the exploitation of temporal inactivity 11, 18, 12, 13, 25, 20, was another improvement. The stiffness [3]of the circuit differential equations has the effect that during intervals of the simulation time, certain parts of a large digital circuit (blocks) remain inactive and need not be recomputed for these time points, thus reducing the computation load on the CPU.

Exploitation of the particular characteristics of special circuits like MOS VLSI has led to further improvements on the computational time. The strong diagonal dominance [16]of the matrix equations of MOS circuits allows these simulators to employ faster equation solution methods 10, 6, 22, but at the cost of limiting either the accuracy of the results or the scope of the circuit categories to be validly simulated.

The only way to further speed up the simulation process without sacrificing the solution accuracy or the range of candidate circuits is either to use a faster algorithm or to use higher performance computers [17]. This paper describes a robust Parallel Circuit Simulator – PARCIS – designed for a message passing multiprocessing system. It uses a demand driven technique, based on the analysis of hierarchically partitioned circuits. This was made possible by developing a method that allows the decoupling of the circuit equations, without loosing accuracy, into hierarchically partitioned blocks and which method further allows the compression of block data. By distributing the computational load and by exploiting the temporal block inactivity (latency) it becomes feasible to get accurate circuit responses in reasonable time. It is noted that PARCIS is:

• (a) a robust simulator, in the sense that it uses a direct solution method for the circuit equations so that its speed or accuracy are not hindered by the circuit category or the degree of coupling between sub-circuits, and

• (b) a fully electrical simulator, because it can simulate all primitive electrical devices like inductors, capacitors, transistors etc.

The rest of the paper is organized as follows. Section 2is dedicated to the theoretical aspects of partitioning and computing the circuit equations. In Section 3, the structure of this simulator is explained briefly. In Section 4, implementation issues and performance results obtained by running various circuit examples in a transputer system, are presented. Section 5concludes the paper and outlines the future directions.