A prototype of a VHDL-based fault injection tool: description and application

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Abstract

This paper presents the prototype of an automatic and model-independent fault injection tool, to be used on an IBM-PC (or compatible) platform. The tool has been built around a commercial VHDL simulator and it is thought to implement different fault injection techniques. With this tool, a wide range of transient and permanent faults can be injected into medium-complexity models. Another remarkable aspect of the tool is the fact that it can analyse the results obtained from injection campaigns, in order to study the Error Syndrome of the system model and/or validate its fault-tolerance mechanisms. Some results of various fault injection campaigns carried out to validate the Dependability of a fault-tolerant microcomputer system are shown. We have analysed the pathology of the propagated errors, measured their latencies, and calculated both error detection and recovery latencies and coverages.

Introduction

One of the main problems of developing and exploiting modern dependable systems is their validation. This is because, in addition to the functional aspect, the correct operation of the fault-tolerance mechanisms (FTMs) must also be considered. The validation of the system coverage depends strongly on the coverages of the various FTMs [1].

The complex behaviour of real fault-tolerant systems (FTSs) implies that their validation needs to be partially experimental, because of [2], [3]:

  • The highly specialised and novel nature of the system components, both hardware and software. Moreover, FTSs are normally used in specific applications, and so few units exist. This hinders the availability of experimental data related to their function.

  • The uncertainty of fault pathologies, mainly about how to quantify the influence of faults on system Dependability.


Experimental validation can be carried out in two different ways [2]:

  • Observing the behaviour of the system in presence of faults during its operative phase, extracting real measures of coverage coefficients, number of failures, and the temporal cost of maintenance operations.

  • By means of controlled experiences, analysing the behaviour of the system in presence of faults introduced deliberately.


The first technique obtains real values for the studied parameters. However, in most cases it cannot be used, because to obtain statistical values with a suitable confidence margin, the observation time required to study the occurrence of all the working possibilities is too long.

For this reason, the second method, called fault injection, is more suitable to validate FTSs. In fact, fault injection is being increasingly consolidated and applied in a wide range of fields, and several automatic tools have been designed [4], [5]. Fault injection technique is defined as follows [2]:

Fault injection is the validation technique of the Dependability of Fault-Tolerant Systems which consists in the accomplishment of controlled experiments where the observation of the system's behaviour in presence of faults is induced explicitly by the written introduction (injection) of faults in the system.

As Fig. 1 shows, fault injection techniques in the hardware of a system can be classified in three main categories [4], [5], [6], [7]:

  • Physical fault injection (hardware implemented fault injection, HWIFI): This is achieved at the physical level, disturbing the hardware with parameters of the environment (internal) or modifying the value of the IC pins (external).

  • Software implemented fault injection (SWIFI): The objective of this technique consists of reproducing at software level the errors that would have been produced if faults occurred in both the hardware and software. This is based on different practical types of injection, such as modification of memory data, or mutation of either the application software or the lowest service layers (at operating system level, for example).

  • Simulated fault injection: In this technique, a model of the system under test, which can be developed at different abstraction levels, is simulated in another computer system. Faults are induced by altering the logical values of the model elements during the simulation.


During the design phase of a system, simulation is an important experimental way to get an early measure of the Performance and Dependability. Another interesting advantage of this technique respect to other injection techniques is the high observability and controllability of all the modelled components.

This paper describes a tool for injecting faults in VHDL1 simulation models. The objective has been to have a tool that complements other fault injection techniques implemented by our research group (AFIT [8] for pin-level HWIFI, and SOFI [9] for SWIFI). This tool is thought to work with models at gate, register and chip level described using the VHDL language. In the context of VHDL-based fault injection tools, we have tried to introduce some specific characteristics. The tool works in a PC (or compatible) under WindowsTM. This leads to a simple and easily portable tool, suitable for injection campaigns in medium complexity systems. Besides these, other objectives have been to implement different types of FTS analysis and to improve some features usually not so much developed in other fault injection tools: fault models and the integration of different VHDL-based fault injection techniques.

The distribution of this paper is as follows. In Section 2 we explain some VHDL simulation-based fault injection techniques that we have used in the experiments, remarking our implementation contributions. Section 3 describes the fault injection tool, showing briefly its components and its more relevant features. In Section 4 we illustrate the fault models used in the injection tool. In Section 5 we present some experiments that show the capabilities of the tool. Finally, in Section 6 we indicate some general conclusions and future enhancements of the tool.

Section snippets

VHDL-based fault injection

VHDL has become one of the most suitable hardware description languages from the point of view of fault injection [10]. The reasons for the success of VHDL can be summarised as:

  • It promotes an open standard for digital design specification.

  • It allows to describe a system at different abstraction levels, as it is possible to make behavioural and structural descriptions.

  • Some elements of its semantics (such as resolution functions, multivalued types, and configuration mechanisms) can be used in

The fault injection tool

Given the usefulness of VHDL-based fault injection for early validation during the design phase, the GSTF has built an injection tool using this method. The general objective is to apply in an automatic way the fault injection techniques in an specific VHDL model.

Firstly, we will study shortly other VHDL injection tools, to know the state of the art of the subject. From this analysis we have developed our tool, introducing new characteristics.

Fault models

We have aimed to use a variety of fault models that would represent real physical faults that occur in ICs. Although the most used models are stuck-at (0,1) (for permanent faults) and bit-flip (for transient faults), as VLSI ICs integration density rises, it becomes more necessary to introduce newer, more complex models. Table 3 summarises the fault models that we have applied in every injection technique.

Fault models for simulator commands and saboteur techniques have been deduced from the

Application of the injection tool

In this section, we will briefly describe an example of model system to be injected, and some significant experiments that show the capability of the tool.

Summary

In this work, a VHDL-based fault injection tool to run on PC platforms is shown, describing its main components and overall performance. The tool is easy to use, versatile, and appropriate to medium-complexity system models.

We have verified the usefulness of the tool carrying out a number of injection experiments using various injection parameters, and performing different types of analysis.

Specifically, we present an injection campaign into a VHDL model of a 16-bit fault-tolerant microcomputer

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