An improved register–transfer level functional partitioning approach for testability¹

Abstract

This paper presents an improved register–transfer level functional partitioning approach for testability. Based on an earlier work (X. Gu, K. Kuchcinski, Z. Peng, An efficient and economic partitioning approach for testability, in Proceedings of International Test Conference, Washington DC, 1995.), the proposed method identifies the hard-to-test points initially based on data path testability and control state reachability. These points will be made directly accessible by DFT techniques. Then the actual partitioning procedure is performed by a quantitative clustering algorithm which clusters directly interconnected components based on a new global testability of data path and global state reachability of control part. After each clustering step, we use a new estimation method which is based partially on explicit re-calculation and partially on gradient techniques for incremental testability and state reachability analysis to update the test property of the circuit. This process will be iterated until the design is partitioned into several disjoint sub-circuits and each of them can be tested independently. The control part is then modified to control the circuit in normal and test mode accordingly. Therefore, test quality is improved by independent test generation and application for every partition and by combining the effect of data path with control part. Experimental results show the advantages of the proposed algorithm compared to other conventional approaches.

Introduction

The development of VLSI technology has brought with it many testing problems. To solve these problems, various approaches have been proposed to enhance the testability of VLSI circuits by incorporating extra testability features. Scan design is a very popular approach which improves the testability by increasing the controllability and observability of the memory elements of sequential circuits 10, 32, 34, 35. In the scan technique, the memory elements are configured into a shift register during testing in order to control as well as observe their states. However, scan design usually introduces a significant area and delay overhead due to the multiplexers in the scan latches and the routing area for the scan chains and the extra inputs. To minimize these overheads, some approaches are based on the concept of partial scan where only a few selected latches are scanned 3, 4, 15, 27, 33. These testability features such as scan are usually incorporated in a post-synthesis step. As the performance and quality requirements of VLSI circuits increase, these DFT methods of improving testability become less attractive due to their unacceptable area and performance overheads.

Different from the above techniques, Synthesis for Testability (SFT) considers testability of the circuits from the early stage of the synthesis process. The overhead due to testability improvement can be reduced by using SFT techniques, since there is a greater flexibility in the design options during the early design stages, and the synthesis process can be guided towards a more testable design. Gebotys et al., [9]and Mujumdar et al. [24]target full or partial scan path techniques during data path allocation to improve testability. Papachristou et al. 25, 26, Flottes [7]and Avra [2]minimize the number of loops for BIST during the allocation phase. Harris et al. [17], Yang et al. [37]and Parulkar [28]have presented integrated scheduling and allocation methods that improve the test quality or reduce the BIST area overhead and resources. Lee et al. 20, 21employ behavioral synthesis rules to ease test generation and therefore improve testability.

In most of these SFT techniques, test generation is still performed as a post-synthesis step and will take a significant amount of the overall design time. Partitioning for a design can lead to the simplifications of many design procedures such as synthesis and test. Partitioning for testability will lead to the simplification of Automatic Test Pattern Generation (ATPG) and the ability to apply different test strategies to different partitions. The proposed partitioning technique transforms some hard-to-test registers and/or lines to boundary components. These components act as normal registers and/or lines in the normal mode and serve as partitioning boundaries in test mode. Therefore, a design is partitioned into several sub-circuits and each of them can be tested and controlled. It is, therefore, possible to apply different test strategies, such as scan for deterministic and BIST for random test to different partitions.

The circuit partitioning problem can, in general, be formulated as a graph partitioning problem. Given a graph with nodes and arcs, the objective is to partition the nodes into several subsets, such that the total costs of the arcs between nodes in different partitions is minimized. Optimal partitioning is known to be NP-complete [8]. Recent work on partitioning for testability has been reported in 1, 5, 13, 16, 23. These papers underline the different aspects which can influence the testability of a design. De and Banerjee [5]present a technique which ensures the minimal number of redundant faults after resynthesizing each partitioned block and subsequent re-connection. Maxii and Meo [23]guarantee that each partitioned block is a fanout free region. In [1], Abadir and Newman partition a design to ease testing, but do not take into account whether the partitioning will result in the optimal or near-optimal solution for testability. The depth-first strategy they use to search adjacent cells to be in the same cluster does not guarantee the best testability after partitioning. In [16], Gupta et al. partition a design by clustering gates to clouds. During clustering, testability issue is not considered. Since full scan is used in their approach, all clouds are combinational.

Recently, Gu et al. [13]have proposed an efficient and economic partitioning approach for testability. The data path is partitioned at some hard-to-test points detected by an RT level testability analysis algorithm. These points are then made directly accessible by DFT techniques. The control part is also modified to control the circuit in normal mode and test mode. However, the heuristics used for partitioning are too fuzzy to be applied for boundary components selection in large circuits. Further a testability analysis algorithm of data path is used to guide the selection of partitioning boundaries. After the initial selection, updating the test property of the circuit is not carried out. Additionally, to control and observe a data path, we need not only to take care of its controllability and observability, but also to move the control part from a given state to another state, since the control states determine when data transfers in the data path take place. Therefore, the state reachability has the same importance as the controllability and observability of the data path for high test quality.

In this paper, we present an improved register-transfer level partitioning approach for testability based on [13]. It is based on a testability analysis algorithm [12]with an incremental testability analysis approach 36, 38for data path and a state reachability analysis algorithm [14]with its incremental analysis approach for control path at register-transfer level. Initially we use the testability algorithm for data path and state reachability algorithm for control part to find partitioning boundaries. Then the partitioning procedure is performed quantitatively by a clustering algorithm which clusters directly interconnected components excluding boundary components based on the global testability of data path and global state reachability analysis of control part. After each selection step, we use a new and efficient estimation method which is based partially on explicit re-calculation and partially on gradient techniques for incremental testability and state reachability to update the test property of the circuit. This process will be iterated until the design is partitioned into several disjoint subcircuits and each of them can be tested independently.

In our approach, the design is only functionally partitioned which means that operations in different partitions can still be allocated to the same physical component in the late design stages. As a result, this approach gives the synthesis tool more flexibility to make trade-offs between the level of parallelism and the area overhead. When a physical component belongs to several partitions, it will be tested several times because we need to test all these partitions. However, we can also eliminate some test vectors which are duplicated for testing the same component.

The paper is organized as follows. Section 2and Section 3describe briefly the design representation and the testability and state reachability analysis algorithm [12], respectively. The corresponding incremental testability and state reachability are described in Section 4. The partitioning algorithm will be presented in two parts, data paths partitioning and control part modification and implementation, in Section 5. Some experimental results compared to other conventional approaches are presented in Section 6. Finally we offer some conclusions and remarks in Section 7.