Hamming weight pyramid – A new insight into canonical signed digit representation and its applications

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Abstract

Signed-power-of-two terms are widely used in design automation algorithms for digital filter synthesis and optimization, linear transformation and other multiple constant multiplication problems. In these applications, the computation efficiency or solution quality tends to degrade with the number of nonzero digits in the signed digit representation of the a priori fixed coefficients. This paper provides a new perspective to interpret the hamming weights of fixed-point coefficients represented in signed-power-of-two terms with minimal number of nonzero digits, called the minimal signed digit (MSD) representation. A new hamming weight pyramid (HWP) is proposed to succinctly compress the information about the distribution of the hamming weights of canonical signed digit (CSD) representation in a visually appealing manner for analysis and synthesis. CSD is a unique and popularly used subset of the general MSD representation. Many interesting properties of CSD are uncovered in this regularly structured HWP. These properties are exploited to develop a novel and elegant algorithm for the direct conversion of decimal number to CSD representation. We also show that the HWP can also be employed to overcome the limit imposed on the word length of the coefficients for the reduced adder graph (RAG) algorithm and filter coefficient synthesis.

Introduction

The use of transformations in high-level synthesis of VLSI circuits has led to the development of powerful optimization methods for many computation intensive digital signal processing tasks. One such class of computational transformation is the multiple constant multiplication (MCM), which found applications in digital filters, convolution, linear transforms, etc. [1], [2], [3], [4]. MCM circuits are dominated by the number of additions and subtractions that compose the set of constant multipliers. While the multiplication of variable by constants appears only in small fraction of general computation benchmarks, its frequency of encounters has been significant in application specific FIR and IIR filters. A dichotomy of design automation algorithms to these application specific problems is that of coefficient synthesis [5], which focuses on minimizing the number of signed-power-of-two (SPT) terms for given transfer function specifications subjected to the constraints of the number of coefficients and their word lengths, and the common subexpression elimination [1], [2], [4], [6], [7], which aims at optimizing the hardware cost, delay and power consumption through maximizing the sharing of resources. The ramification is that the encoding of the coefficients plays an important role in the optimality of the MCM solutions and the efficiency of the design automation algorithms. Canonical signed digit (CSD) representation, which is a special subset of the minimal signed digit (MSD) representation, has been used with phenomenal success in reducing the complexity of MCM circuits. CSD has even been successfully employed in programmable FIR filter to improve its area efficiency [3]. This paper presents a new formulation of a triangular tree structure to analyze the hamming weights of CSD numbers. Since CSD and MSD representations of specific number share the same hamming weight, the structure may also apply on MSD. The goal is to uncover interesting properties that can be exploited for computational transformations to MCM problem.

A signed digit representation [8] of radix r is a positional number system with a symmetrical digit set, i.e., a = (an−1,  , a2, a1, a0) with ai  {0, ± 1, ± 2,  , ± (r  1)}. Signed digit representations of radix 2 are widely used for digital arithmetic operations, such as Booth encoding and modified Booth encoding [9], [10]. A signed digit representation is said to be minimum if it possesses the minimal hamming weight. MSD representations [11] are crucial in reducing the hardware cost and power consumption in many complex arithmetic operations. The CSD form [12], and the generalized nonadjacent form (GNAF) [11], [13], are the specific MSD representations for radix 2 and general radix r > 2, respectively. Both CSD and GNAF are unique and have no adjacent nonzero digits in their positional notations. Any arbitrary n-bit 2’s complement number can be represented in CSD form with no more than (n + 1)/2 nonzero digits. It was shown in [14] that the expected number of nonzero digits in an n-digit CSD number tends asymptotically to n/3 + 1/9. On average, CSD uses 33% fewer nonzero digits than the normal binary number. The finite spaces of u terms power-of-two integers have been discussed in [15].

To generate a CSD number, usually the decimal number needs to be converted to the binary form first. The traditional approach [16] to generate the CSD number from the binary form uses lookup table. Other algorithms for the conversion of the binary to SD [16] representations involve the computation of interim difference and 2’complement to CSD by applying T2I conversion (conversion of a number to its inverse-2’s complement format) partially or searching for the nearest SPT term [9], [15]. Some methods have also been developed to generate MSD and signed digit representations with the number of nonzero digits more than the minimal hamming weight [1], [17], [18], [19]. Recently, some new approaches based on look-ahead circuits [10], [20] and different derivations of CSD [9], [21] have been reported to circumvent the conversion problem. The dominance of conversion algorithms to CSD based on normal binary instead of decimal number can be easily understood as binary arithmetic prevails in typical digital computers. Recently, IBM developed the first decimal arithmetic processor, eServer z900 to perform decimal instructions in hardware [22], [23]. The direct conversion from decimal number to CSD will benefit from the decimal arithmetic unit of IBM eServer z900 as its decimal computation capability is limited to integer operands. The significance and interest in decimal arithmetic has also led to a proposed revision to the IEEE 754 standard for FP arithmetic to include specifications for decimal arithmetic specifications [24]. On the other hand, in design automation algorithms leading to efficient digital filter design [2], [4], [6], [7], the original constant coefficients are normally derived in decimal (integer) form and it would be useful to interpret the CSD number and its conversion directly from the decimal form. Besides, there exist a number of algorithms [5] for synthesizing signed digit coefficients to map the infinite precision filter coefficients into finite length coefficients so that fewest possible SPT terms are used to meet the design specifications. The hamming weight of a multiplicand decides the number of adders needed, and hence the complexity of the circuits. The characteristics of the hamming weights of the CSD numbers can be exploited to enhance their computation efficiency and performance.

In this paper, we provide a new insight into the formation of the CSD numbers. We derive a unique regular structure of the hamming weights of the CSD numbers and name it the hamming weight pyramid (HWP). The notion of HWP was first introduced in [25], and more elaborated properties and applications are extended here. Many useful and attractive properties are extracted from the HWP. A reduced HWP is also proposed. It can be constructed easily from a reduced-size lookup table. From the properties of the HWP, a new method to convert decimal number to its CSD format is derived with the computation complexity compatible to that of the conversion from decimal number to binary number. Direct conversion from decimal number to CSD form without an intermediate redundant signed digit number conversion step makes it attractive for many design automation algorithms that can be benefited from the substitution of integer operations by their CSD forms. The proposed conversion method from the HWP induces a new CSD tree (CSDT). This CSDT provides a more straightforward view of the conversion from decimal number to CSD representation. The HWP is also employed to devise the cost metric of a recently proposed decimal number-based algorithm, MRAG [26] to extend the word length of the coefficients managed by the n-dimensional reduced adder graph (RAG-n) [27] algorithm. For filter coefficient synthesis problem, HWP can also be used to guide the minimization algorithm for reducing the total number of SPT terms in the coefficient set subjected to some maximal permissible frequency response error.

Section snippets

The hamming weight pyramid (HWP)

To reduce the implementation cost of compound arithmetic operations by using simple addition, subtraction and shift operations in conventional binary computer, the 2n + 1 distinct integers, X in the range of (−2n + 1, 2n + 1) are generally represented with signed digit (SD) representation as follows [14], [16]:X=i=0nai2i,ai{0,±1}

The hamming weight of the SD is defined as the number of nonzero digits, ai in (1). A canonical signed digit (CSD) representation is a unique SD representation that

Properties of HWP

The CSD represented numbers, 2i with the hamming weight of 1, form the middle pillar of the HWP, from which symmetrical number of entries are extended on both sides. The leftmost entry of any arbitrary row represents the hamming weight of a CSD number adjacent to one corresponding to the rightmost entry of the row above it. This formation has led to several interesting properties.

Property 1

The CSD numbers corresponding to row i of the HWP are the range of natural numbers that can be represented with i + 1

Decimal to CSD conversion

The HWP provides a new perspective to the synthesis of CSD numbers. With the help of Property 3 and Eq. (3), we develop the following algorithm for the conversion of a decimal number, d to its CSD representation, csd. The pseudo-code in Fig. 9 describes the algorithm.

In Fig. 9, the function row_number(d) searches for the row index, i such that S(i  1) < d  S(i). The conversion requires h iterations to complete where h is the hamming weight of csd. Thus, the average number of iterations for an n

Use of HWP in MRAG

Among all common subexpression elimination algorithms applied to the synthesis of digital filter coefficients for multiple constant multiplication circuits, the solutions produced by the n-dimensional reduced adder graph (RAG-n) [27] usually have the least logic complexity. One of the major contributing factors RAG-n possessed over similar algorithms is the concept of adder cost, which is the least number of adders used to implement a single coefficient. To obtain the optimal cost of each

Conclusions

CSD representation plays a major role in MCM problems and optimization algorithms for FIR and IIR filters [2], [4], [5], [6], [7]. A good understanding of the specific properties exhibited by these numbers and their appropriate exploitation may help to improve the quality and efficiency of existing algorithms, or even lead to new concepts and new algorithms. In this paper, we have proposed a regularly structured hamming weight pyramid (HWP) to assist us in exploring the interesting properties

Fei Xu received her B.Eng. in Electronic Engineering from Zhe Jiang University, China in 2002 and she is a PhD student in the School of Electrical and Electronic Engineering of Nanyang Technological University, Singapore. She is currently working as a Test Software Engineer in Xilinx Asia Pacific Pte. Ltd. Her current research interest includes digital filter design, and CAD for VLSI.

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  • Cited by (0)

    Fei Xu received her B.Eng. in Electronic Engineering from Zhe Jiang University, China in 2002 and she is a PhD student in the School of Electrical and Electronic Engineering of Nanyang Technological University, Singapore. She is currently working as a Test Software Engineer in Xilinx Asia Pacific Pte. Ltd. Her current research interest includes digital filter design, and CAD for VLSI.

    Chip-Hong Chang received his B.Eng. (Hons) from National University of Singapore in 1989, and his M.Eng. and PhD from the School of Electrical and Electronic Engineering of Nanyang Technological University, Singapore in 1993 and 1998, respectively. He worked as a Component Engineer of General Motors, Singapore in 1989 and as technical consultant of Flextech Electronics Pte. Ltd. in 1998. He joined as a Lecturer in the Electronics Design Centre of Nanyang Polytechnic in 1993. Since 1999, he has been with the School of Electrical and Electronic Engineering, Nanyang Technological University where he is currently an Associate Professor. He has served a number of administrative and consultation roles during his academic career. He holds concurrent appointments at the university as the Deputy Director of the Centre for High Performance Embedded Systems (CHiPES) since 2000, and the Program Director of the VLSI Design and Embedded Systems research group of the Centre for Integrated Circuits and Systems (CICS) since 2003. His current research interests include low power arithmetic circuits, algorithms and architectures for digital signal processing. He has published three book chapters and more than 120 research papers in international refereed journals and conferences. He is a senior member of the IEEE.

    Ching-Chuen Jong received the B.Sc. (Eng) degree in Electronics with Computer Science and the PhD degree in Electronic Engineering from Queen Mary London, UK, in 1983 and 1988 respectively.

    From July 1987 to October 1990, he worked in the area of high-level synthesis of digital systems first in academic then in industrial in UK. In 1991, he joined the Nanyang Technological University, Singapore, as a faculty member. He is now an Associate Professor in the Division of Circuits and Systems, School of Electrical and Electronic Engineering. Dr. Jong is a Chartered Engineer, a member of IET and a member of BCS. His technical interests include high-level synthesis, ASIC design and fast-prototyping of digital designs.

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