Optically injected logic circuits for remote-powered systems on a chip,☆☆

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Abstract

This paper reviews the concept of optically injected logic circuits and investigates their implementation in nanometer CMOS technologies. Optically injected circuits are powered via an optical beam, i.e. they do not require a local power supply and distribution network. A complete set of digital cells has been designed and simulated, and key building blocks of the logic family have been fabricated and tested in a standard 180 nm CMOS technology. The paper also discusses the design and implementation of optically injected circuits for clock distribution, input/output, analog-to-digital and digital-to-analog conversion. All these circuits are immediately applicable in wireless biomedical implants or contactless smart cards. They can also be used in other systems-on-chip (SoC), in which very low power operation can be replaced by remote-powered operation.

Introduction

Low-power operation can be replaced with remote-powered operation for applications such as wireless biomedical implants and contactless smart cards. Wireless biomedical implants are remotely powered using electromagnetic-field coupling [1], [2], [3], [4], [5], [6], [7], [8], [9], or an ultrasound beam [10], [11]. Contactless smart cards are remotely powered using electromagnetic-field coupling [13], [14]. Alternatively, thermal energy can be harvested as described by Lhermet et al. [15], or power can be generated from vibrations as investigated by Amirtharajah and Chandrakasan [16].

In general, remote-powered operation requires a reader or an external device, hereafter the interrogator, to deliver the necessary energy to the interrogated device, hereafter the target, via electromagnetic-field coupling or an ultrasound beam, as shown in Fig. 1a and b, respectively. For subcutaneous biomedical implants, Murakawa et al. have shown in Ref. [17] that energy transfer is also possible via an optical beam (see Fig. 1c). Electromagnetic-field coupling requires the interrogator and the target to be in the proximity of a few centimeters. Ultrasound or optically beamed energy requires line of sight between the interrogator and the target, but the distance can be increased by collimating and increasing the power of the beam.

As pointed out by Puers [12], miniaturization is a key requirement for these applications. Current targets need to integrate inductor coils or loop antennas on the order of a few cm2 (see Fig. 1a) or an ultrasound transducer (see Fig. 1b) or an array of photovoltaic cells (see Fig. 1c). In addition, a dc–dc converter and a power distribution grid are also required. In support of miniaturization, we propose to implement the target circuitry using optically injected circuits, thus eliminating the need for the array of photovoltaic cells, dc–dc converter, and power distribution grid (see Fig. 1d).

Integrated injection logic circuits (I2L) were first described and implemented by Hart and Slob [18], and Berger and Wiedmann [19]. The history of these two independent inventions was later captured by Guterl [20]. Integrated injection logic circuits use a current source to inject charge into a logic circuit node. The injector or current source is a forward biased p–n junction diode (see Fig. 2b) which has been used in bipolar technologies during the ‘70’s and ‘80’s, [21], [22], [23], [24], [25]. Using an enhancement-mode MOSFET as current injector, Wu et al. have proposed in Ref. [26] an equivalent logic in CMOS, which they called multi-drain logic. Integrated injection logic has also been implemented in SiGe, GaAs, and other III–V semiconductor technologies [27], [28], [29], [30], [31], [32], [33], [34], [35], and is appealing for logic circuits operating at high temperatures [36], [37].

Of significance for the work we present is the fact that Hart and Slob [18] have also described and implemented circuits in which they replaced the current injector as a p–n junction diode irradiated with light of a suitable wavelength (see Fig. 2b). The p–n junction diode was the base-emitter junction of an n–p–n bipolar transistor (see Fig. 2c). In their implementation the transistors act as current sources and inverters, and the other logic functions are implemented by wiring the collectors. In the presented work we build on this topology by using NMOS transistors as inverters, a large p+/n-well diode as current source (see Fig. 2d) and wired drains to implement the other logic functions.

Hence, in current-mode logic, when the switch is off, the charge is used as source current to turn on the next switch. When the switch is on, the current is sunk to ground and turns off the next switch. In voltage-mode logic, when the switch is off, the charge is used to charge the output node capacitance and a voltage higher than the threshold voltage turns on the next switch. When the switch is on, the output node is pulled to ground and turns off the next switch. The switch in current-mode logic is an n–p–n bipolar transistor, and in voltage-mode logic an NMOS transistor.

In this paper we report the design and evaluation of optically injected logic circuits and associated clock distribution network in a 180 nm standard CMOS technology. We further investigate the implementation of optically injected interface and mixed-signal circuits. All these circuits are immediately applicable to the design of wireless biomedical sensors and smart cards.

In Section 2 we cover optically injected logic circuits in CMOS, followed by clock generation and distribution in Section 3, and interface and mixed-signal circuits in Section 4.

Section snippets

Optically injected logic circuits in CMOS

In this section we first present the gate topologies of optically injected logic circuits. Then we describe the process and considerations for component sizing. Next we characterize the logic circuits. We complete the section with the design and simulation of the basic memory element: the D-latch.

Clock generation and distribution

Synchronous sequential logic circuits require a clock to be distributed over the area of the circuit for proper operation [39]. Considering the total area of a gate, including the routing channels (see Fig. 9) a low complexity system using ∼20,000 gates will cover a square area of about 3 × 3 mm2, while a high complexity system using 1 million gates will cover an area of about 20 × 20 mm2. The optically injected logic circuits described in the previous section operate at a maximum clock frequency of 10

Interface and mixed-signal circuits

To complement the capabilities of the system embedded in the target in Fig. 1, we evaluate in this section the design and implementation of interface and mixed-signal circuits that would be compatible with the optically injected logic circuits described before.

Conclusions

Optically injected logic circuits in nanometer CMOS technologies have been designed and evaluated. Implementation issues have been discussed, solutions have been proposed and logic characterization has been performed. Mixed-signal circuits necessary for full implementation of a system-on-chip have been analyzed and designed. Measurements of photovoltaic cells, photo-detectors and light emitting devices in a 0.18 μm CMOS technology have been used to predict the performance of future application

Acknowledgment

Fabrication was sponsored through the MOSIS MEP Research Program. During the course of this work, Dorin Patru was supported through several Teaching and Research Assistantships by the Electrical Engineering and Computer Science Department at Washington State University and by an NSF CRCD grant. Special thanks go to: John Yates who has provided important logistical support during the measurements, to the IT personnel of the WSU/EE department, and to Sean O’Brian of RIT/SMFL for assistance with

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    Reviews processed and proposed for publication to the Editor-in-Chief by Associate Editor Dr. F. Sahin.

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    This work was supported in part by the MOSIS MEP Research Program and by an NSF CRCD grant.

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