Test data compression based on geometric shapes

Abstract

The increasing complexity of systems-on-a-chip with the accompanied increase in their test data size has made the need for test data reduction imperative. In this paper, we introduce a novel and efficient test-independent compression technique based on geometric shapes. The technique exploits reordering of test vectors to minimize the number of shapes needed to encode the test data. The test set is partitioned into blocks and then each block is encoded separately. The encoder has the choice of encoding either the 0’s or the 1’s in a block. In addition, it encodes a block that contains only 0’s (or 1’s) and x’s with only 3 bits. Furthermore, if the cost of encoding a block using geometric shapes is higher than the original cost of the block, the block is stored as is without encoding. The effectiveness of the technique in achieving high compression ratio is demonstrated on the largest full-scanned versions of ISCAS89 benchmark circuits. The proposed technique achieves significantly higher compression in comparison to other test-independent compression techniques reported in the literature.

Introduction

With today’s technology, it is possible to build complete systems containing millions of transistors on a single chip. Systems-on-a-chip (SOC) are comprised of a collection of pre-designed and pre-verified cores and user defined logic (UDL). As the complexity of systems-on-a-chip continues to increase, the difficulty and cost of testing such chips is increasing rapidly [1], [2]. To test a certain chip, the entire set of test vectors, for all the cores and components inside the chip, has to be stored in the tester memory. Then, during testing, the test data must be transferred to the chip under test and test responses collected from the chip to the tester.

One of the challenges in testing SOC is dealing with the large size of test data that must be stored in the tester and transferred between the tester and the chip. The amount of time required to test a chip depends on the size of test data that has to be transferred from the tester to the chip and the channel capacity. The cost of automatic test equipment (ATE) increases significantly with the increase in their speed, channel capacity and memory. As testers have limited speed, channel bandwidth and memory, the need for test data reduction becomes imperative. To achieve such reduction, several test compaction and lossless compression schemes were proposed in the literature.

The objective of test set compaction is to generate the minimum number of test vectors that achieve the desired fault coverage. The advantage of test compaction techniques is that they reduce the number of test vectors that need to be applied to the circuit under test while preserving the fault coverage. This results in reducing the required test application time. However, as shown in [3], detecting a fault multiple times increases the defect coverage. Thus, test set compaction while preserving the fault coverage may reduce the physical defect coverage.

In test data compression, the objective is to reduce the number of bits needed to represent the test data. For test data compression, it is essential that the compression is lossless. Run length coding, Huffman codes, Lempel–Ziv algorithms, and arithmetic codes are examples of lossless compression [4]. Several test data compression techniques were proposed in the literature. These techniques can be classified into two categories; those that require structural information of the circuit and rely on automatic test pattern generation and/or fault simulation and those that are more suitable for intellectual property (IP) cores as they operate solely on the test data. Techniques of the first approach include some of the linear decompression-based schemes [5], [6], [7] and broadcast-scan-based schemes [8], [9], [10]. Techniques of the second approach include statistical coding [11], [12], selective Huffman coding [13], run-length coding [14], mixed run-length and Huffman coding [15], Golomb coding [16], frequency-directed run-length (FDR) coding [17], alternating run-length coding using FDR (ALT-FDR) [18], extended frequency-directed run-length (EFDR) coding [19], MTC coding [20], variable-input Huffman coding (VIHC) [21], multilevel Huffman coding [22], 9-coded compression [23], Block Merging (BM) compression [24] and dictionary-based coding [25], [26]. Test compression techniques in this class can be further classified as being test independent or test dependent. Test-independent compression techniques have the advantage that the decompression circuitry is independent of the test data. Changing the test set does not require any change to the decompression circuitry. Examples of test-independent compression techniques include Golomb coding [16], frequency-directed run-length (FDR) coding [17], alternating run-length coding using FDR (ALT-FDR) [18], extended frequency-directed run-length (EFDR) coding [19], MTC coding [20], 9-coded compression [23] and Block Merging (BM) compression [24]. While most compression techniques are based on a test decompression circuitry on chip, several test data compression techniques which perform decompression of test data based on an embedded processor were proposed in [27], [28], [29], [30].

The majority of the proposed compression techniques rely on the fact that test sets contain a large number of X’s. Efficient test relaxation techniques for combinational and sequential circuits have been recently proposed in [31], [32], [33]. It is shown in [31] that for highly compacted test sets by Mintest [34] a large percentage of X’s is extracted for most circuits.

In this paper, we introduce a novel and efficient test-independent compression scheme based on geometric shapes, initially presented in [35]. The scheme is based on test data sorting to minimize the number of shapes needed to encode the test set. Test data is partitioned into blocks and each block is encoded separately. Test vector decompression is performed on chip and is implemented either in hardware or software. For hardware decompression option, a decoding circuitry is placed on the chip to perform the decompression algorithm. However, for software decompression option, an embedded core is used to execute the decompression algorithm and decompress the test data, which is then applied to the circuit under test. The decompression algorithm can be stored in a ROM on the chip.

The rest of this paper is organized as follows. In Section 2, the proposed test encoding algorithm is described. The test data decoding process and decompression using both hardware and software solutions are presented in Section 3. In Section 4, experimental results are given to illustrate the effectiveness of the proposed compression technique and a comparison is made with other test-independent compression techniques. Finally, Section 5 concludes the paper.