An efficient control-flow checking technique for the detection of soft-errors in embedded software

Abstract

In this paper, we propose a new technique to improve the efficiency of control-flow checking for detecting soft-errors in embedded software. The novelties of the proposed technique are as follows: (1) the frequency of used variables and the frequency of the execution of basic blocks are used as two parameters for selecting important variables and basic blocks, (2) kernel blocks (i.e., a subset of the program’s flowgraph vertices) are used for the selection of important basic blocks, and (3) using the proposed method, developers can make a trade-off between the detection latency and the performance overheads. The experimental evaluations using several benchmarks showed that the execution time in the hardened code is less than the relationship signatures for control flow checking (RSCFC) method, while the memory overhead and code size remains nearly the same. The execution time of the hardened code also remains nearly the same as the original code.

Introduction

Embedded computer systems are widely used in safety–critical applications, such as satellites, automotive and airplanes. Faulty behavior of these systems may lead to catastrophic incidents, so they must be designed to detect faults in minimum time. Faults are classified into three categories: permanent, transient and intermittent. Permanent faults result from manufacturing defects or residual design errors in hardware or software components. Transient and intermittent faults are due to environmental effects such as electromagnetic interference and alpha particle hits.

Transient faults or soft-errors have appeared rapidly in software, not only in electronically-spatial systems, but also at ground and sea level. Such faults (e.g., single event upset [1], [2]) cause incorrect execution of statement or modify bit-flips in memory.

Hardware redundancy and radiation hardening are two fault avoidance techniques used in spatial electronic components. However, the major defect of these techniques is performance reduction, high cost, high weight, and power consumption. Also, the lack of using today’s commercial components is another drawback of these techniques [1], [2].

Software implemented hardware fault tolerance (SIHFT) is another approach that uses software fault tolerance techniques for detecting faults in safety–critical systems. These techniques are divided into two classes that tolerate the processor and memory errors. For example, software-implemented error detection and correction (EDAC) [3] is an effective solution that recognizes and restores memory faults. Error detection by duplicated instruction (EDDI) is another technique that defeats processor effective faults [4].

The occurrence probability of transient faults is more than the other faults in the environments like space. Permanent or transient faults in hardware components, such as the program counter and the memory elements, may result in control-flow errors (CFEs). According to several reports in the literature, up to 70% of transient faults lead to CFEs in the program execution [5]. Therefore, it seems that control-flow based methods for checking and showing the solutions for optimization of memory and performance of these methods are important [6].

In this paper, we propose a new technique to improve the efficiency of control-flow checking methods. In the proposed approach, the program code is processed prior to applying the control-flow checking algorithm. The pre-process includes detecting high-frequent used variables and important basic blocks. The def-use chain algorithm is used for detecting high-frequent used variables. Important basic blocks are selected by nominee blocks set, which is based on the concept of kernel [7]. According to [7], a kernel is a subset of the program’s flowgraph vertices with the property that any set of tests which executes all vertices of the kernel executes all vertices of the flowgraph.

The proposed technique can be customized by developers to fulfill the requirements of different applications. After generating this information, the control-flow algorithm is applied to the program code. The novelties of the proposed method are as follows:

• The frequency of used variables and the frequency of the execution of basic blocks are used as two parameters for selecting important variables and basic blocks.

• Kernels are used for the selection of important basic blocks.

• The developer can make a trade-off between the detection latency and the performance overheads based on the sensitivity of software.

The structure of this paper is as follows. Section 2 gives some of the basic concepts used throughout the paper. Some existing techniques for reducing the performance and memory overheads are reviewed in Section 3. Section 4 summarizes the motivations of this work. In Section 5, the proposed technique for applying the method is introduced. In Section 6, the prototype implementation of the proposed technique is presented. The experimental results are given in Section 7. And, finally, the paper is concluded in Section 8.