Variability-aware architecture level optimization techniques for robust nanoscale chip design

Highlights

• Origin and types of process variations in nanoscale circuits are discussed.

• Nanoscale variability aware architectural-level optimizations that improve yield are presented.

• A methodology is proposed to characterize nanoscale components accounting for variability.

• An algorithm is proposed for the reduction of total power accounting for leakage.

• A total power reduction up to 70% with no performance penalty is obtained.

Abstract

The design space for nanoscale CMOS circuits is vast, with multiple dimensions corresponding to process variability, leakage, power, thermal, reliability, security, and yield considerations. These design issues in the form of either objectives or constraints can be handled at various levels of digital design abstraction, such as architectural, logic and transistor. At the architectural level (a.k.a. Register-Transfer Level, RTL), there is a balanced degree of freedom for fast design exploration by exploring various values of design parameters. Correct design decisions at an early phase of the design cycle ensure that design errors are not propagated to lower levels of circuit abstraction, where it is costly to correct them. Moreover, design optimization at higher levels of abstraction provides a convenient way to deal with design complexity, facilitates design verification, and increases design reuse through intellectual property (IP) cores.

To achieve power-performance trade-offs, different architectural-level techniques have been proposed in the existing literature. This paper will briefly discuss selected RTL techniques which account for process variation. These existing approaches handle the optimization of different power components independently but do not effectively account for the inherent variation of process and design parameters. Thus, in this paper, a novel process variation aware statistical RTL optimization approach is presented. Assuming dual values of $T_{\mathit{ox}}\text{,}{V}_{\mathit{th}}$, and $V_{\mathit{DD}}$, gate-oxide leakage, subthreshold leakage, dynamic power, and performance are estimated for architectural units. Statistical variations in the parameters ($T_{\mathit{gate}}\text{,}{V}_{\mathit{th}}\text{,}{V}_{\mathit{DD}}$, and $L_{\mathit{eff}}$), are explicitly taken into account by using Monte Carlo simulations while characterizing the architectural units. The proportion of values of gate-oxide and subthreshold leakage and dynamic power in the total power consumption of these units is then analyzed. This analysis in essence gives a relative and integrated perspective of various power-performance tradeoffs against the baseline case, thus serving as a guideline to help designers make appropriate decisions. Experiments on several benchmarks show a significant reduction in gate-oxide and subthreshold leakage, dynamic, and total power.

Introduction

Consumer electronic systems such as mobile smart phones, media players, high-definition television (HDTV), health monitoring devices, and various sensors have a profound impact on society. The Integrated Circuit (IC) is the main workhorse in consumer electronics [1]. Efficient design of ICs is one key driving factor for their omnipresence, from kitchens to spacecrafts. To meet the growth of ICs, the industry has resorted to aggressive device scaling [2]. It is estimated that one billion transistors per person were manufactured in 2010! Scaling has essentially provided the following advantages: (1) Reduced the cost of computing as a larger number of transistors are being packed in the same area. (2) Reduced the per transistor manufacturing cost. (3) Reduced power dissipation per transistor as smaller transistors need lower operating voltages. However, the overall power dissipation is still a big issue along with the leakage mechanisms. (4) Initiated the multicore era for high performance computing even in mobile platforms as very large numbers of transistors can be packed in the same area. The challenges in nanoscale chip design include the following: variability, leakage, power, thermals, reliability, and yield [3], [4], [5]. Process variations from different sources have a profound effect on power, leakage and delay. The effect of process variations in delay will translate to uncertainty in clock width in multicycle or pipelined datapaths. This paper focuses on the prominent challenges, at the architectural level, for variability-tolerant power (leakage) optimal nanoelectronic chip design.

At present, an increasing number of small and mobile electronic devices (Fig. 1) are being designed, thus heavily relying on battery power for portability. Power dissipation is an important design constraint in high-performance processor systems, system-on-chip (SoC) designs, as well as application specific integrated circuits. To meet the increasing demand of low-power chips with high performance and higher integration density and functionality of digital devices, VLSI design engineers are resorting to relentless scaling in process and design parameters of CMOS transistors. However, this scaling has resulted in a number of new concerns, including a new dimension of leakage current distribution and process variation [6]. The trends of these components are presented in Fig. 2 [7], [2]. Gate-oxide leakage which is dominant in sub-90 nm traditional CMOS, is negligible in the case of high-$\kappa$ based transistors.

The prominent current (power dissipation or leakage dissipation) components primarily depend on gate oxide thickness ($T_{\mathit{gate}}$), threshold voltage ($V_{\mathit{th}}$), supply voltage ($V_{\mathit{DD}}$), and effective device length ($L_{\mathit{eff}}$). Hence, any methodology for power reduction must focus on the variation of these process and design parameters. This focus has been the motivating factor to consider process variation during architectural-level optimization and to facilitate fast and correct design space exploration right at the early stages of the design cycle, targeted for design for manufacturing (DFM). This will ensure that wrong design decisions are not propagated to the lower levels of circuit abstraction, which may be costly to correct at that stage because of increasing complexity [6]. The novel methodology discussed in detail in this paper consistently does so and incorporates directly the variation in the model for various current components.

To achieve power-performance trade-offs, different solutions have been proposed in the architectural-level (or RTL) synthesis and optimization literature and include different technology dependent and technology independent methods. The technology dependent approaches include scaling of various process and design parameters such as $T_{\mathit{gate}}$, $\kappa \text{,}{L}_{\mathit{eff}}\text{,}{V}_{\mathit{th}}$, and $V_{\mathit{DD}}$ through the use of technologies such as dual-$V_{\mathit{DD}}$ and dual-$V_{\mathit{th}}$. These approaches handle the optimization of various components independently and do not address the variation of various process and design parameters in the nano-CMOS regime. The research proposed in this paper is further motivated by these important facts of nanoscale technology based architectural-level design exploration.

The rest of the paper is organized as follows. The novel contributions of this paper are outlined in Section 2. The specific research issues and challenges arising in the nano-CMOS regime are presented in Section 3. Section 4 summarizes relevant prior related research in architectural-level or RTL optimization. The proposed architectural-level solution and optimization problem formulation is presented in Section 5. A new framework for statistical architectural-level optimization needed to handle nano-CMOS regime circuits is presented in Section 6. A few selected prior research papers dealing with process-variations at the architectural-level are briefly discussed in Section 7. The paper concludes in Section 8 with a summary and suggestions for future research.