Variability-aware architecture level optimization techniques for robust nanoscale chip design☆
Graphical abstract
Introduction
Consumer electronic systems such as mobile smart phones, media players, high-definition television (HDTV), health monitoring devices, and various sensors have a profound impact on society. The Integrated Circuit (IC) is the main workhorse in consumer electronics [1]. Efficient design of ICs is one key driving factor for their omnipresence, from kitchens to spacecrafts. To meet the growth of ICs, the industry has resorted to aggressive device scaling [2]. It is estimated that one billion transistors per person were manufactured in 2010! Scaling has essentially provided the following advantages: (1) Reduced the cost of computing as a larger number of transistors are being packed in the same area. (2) Reduced the per transistor manufacturing cost. (3) Reduced power dissipation per transistor as smaller transistors need lower operating voltages. However, the overall power dissipation is still a big issue along with the leakage mechanisms. (4) Initiated the multicore era for high performance computing even in mobile platforms as very large numbers of transistors can be packed in the same area. The challenges in nanoscale chip design include the following: variability, leakage, power, thermals, reliability, and yield [3], [4], [5]. Process variations from different sources have a profound effect on power, leakage and delay. The effect of process variations in delay will translate to uncertainty in clock width in multicycle or pipelined datapaths. This paper focuses on the prominent challenges, at the architectural level, for variability-tolerant power (leakage) optimal nanoelectronic chip design.
At present, an increasing number of small and mobile electronic devices (Fig. 1) are being designed, thus heavily relying on battery power for portability. Power dissipation is an important design constraint in high-performance processor systems, system-on-chip (SoC) designs, as well as application specific integrated circuits. To meet the increasing demand of low-power chips with high performance and higher integration density and functionality of digital devices, VLSI design engineers are resorting to relentless scaling in process and design parameters of CMOS transistors. However, this scaling has resulted in a number of new concerns, including a new dimension of leakage current distribution and process variation [6]. The trends of these components are presented in Fig. 2 [7], [2]. Gate-oxide leakage which is dominant in sub-90 nm traditional CMOS, is negligible in the case of high- based transistors.
The prominent current (power dissipation or leakage dissipation) components primarily depend on gate oxide thickness (), threshold voltage (), supply voltage (), and effective device length (). Hence, any methodology for power reduction must focus on the variation of these process and design parameters. This focus has been the motivating factor to consider process variation during architectural-level optimization and to facilitate fast and correct design space exploration right at the early stages of the design cycle, targeted for design for manufacturing (DFM). This will ensure that wrong design decisions are not propagated to the lower levels of circuit abstraction, which may be costly to correct at that stage because of increasing complexity [6]. The novel methodology discussed in detail in this paper consistently does so and incorporates directly the variation in the model for various current components.
To achieve power-performance trade-offs, different solutions have been proposed in the architectural-level (or RTL) synthesis and optimization literature and include different technology dependent and technology independent methods. The technology dependent approaches include scaling of various process and design parameters such as , , and through the use of technologies such as dual- and dual-. These approaches handle the optimization of various components independently and do not address the variation of various process and design parameters in the nano-CMOS regime. The research proposed in this paper is further motivated by these important facts of nanoscale technology based architectural-level design exploration.
The rest of the paper is organized as follows. The novel contributions of this paper are outlined in Section 2. The specific research issues and challenges arising in the nano-CMOS regime are presented in Section 3. Section 4 summarizes relevant prior related research in architectural-level or RTL optimization. The proposed architectural-level solution and optimization problem formulation is presented in Section 5. A new framework for statistical architectural-level optimization needed to handle nano-CMOS regime circuits is presented in Section 6. A few selected prior research papers dealing with process-variations at the architectural-level are briefly discussed in Section 7. The paper concludes in Section 8 with a summary and suggestions for future research.
Section snippets
Contributions of this paper
In view of the optimization problem of nanoscale circuits at the architectural level (or register-transfer level), while simultaneously accounting for process variations, the following research questions arise:
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How do the architectural-level design phases (e.g. scheduling, binding) affect power, leakage, area, and yield in the presence of variations?
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Given architectural constraints, how to judiciously consider the design corners to obtain a power, leakage, and performance optimal circuit for
The multidimensional issues of architectural-level design
The designers of chips which are targeted to be manufactured using nanoscale technology face a very complex multidimensional design space as presented in Fig. 3 [6], [3].
Overview of prior research in architectural-level optimization
The current literature is rich in techniques for power optimization. These techniques are proposed for various levels of circuit abstraction, starting from system-level to silicon. As the level of abstraction goes lower, the complexity of the circuit increases, and the degrees of freedom, and thus power reduction opportunities, decrease. Hence, behavioral level (also known as high-level or algorithmic level) is an attractive level that provides a balanced degree of freedom for design space
The key concept
The key concept of architectural-level variability aware optimization is presented in Fig. 9 [3], [6]. The major challenges arising in the nano-CMOS variation scenario are the correct understanding of the process variations and their modeling. Without proper models of variations, designers will include a substantial design margin or risk yield loss when they use traditional computer-aided design (CAD) or electronic design automation (EDA) tools that do not account for such variations. The
The proposed RTL optimization flow
We present the overall framework for statistical low-power architectural-level optimization in Fig. 11. The optimization framework assumes a behavioral hardware description language (HDL) as input and generates a statistical power and delay optimal RTL description accounting for process variations. The generated RTL will go through logic and physical synthesis before being realized in silicon, a process which is beyond the scope of this paper. As shown in the figure, the entire behavioral
Approaches for variability aware power and power-fluctuation minimization
One of the earliest approaches for variability aware power (including leakage) optimization at the architectural level is traced back to [50]. In this paper, resources of dual gate oxide thicknesses, dual threshold voltage, and dual power supply are considered. The statistical variations in these parameters are explicitly taken into account by using Monte Carlo simulations to characterize a datapath component library. The overall minimization problem reduces to the minimization of two cost
Summary
The state-of-the art in architectural-level optimization of digital circuits addressing process variation is reasonably mature. Several statistical approaches have been presented to address yield for both power and timing. In particular, timing yield has received more attention. It is observed that, at present, low-power RTL optimization research mostly address dynamic power reduction only, while some works address subthreshold leakage only, and a few address gate-oxide leakage only. All of
Acknowledgements
S.P. Mohanty and E. Kougianos acknowledge NSF award DUE-0942629 for partial support for this paper. Some preliminary results of this research were presented in the conference paper [50].
Saraju P. Mohanty is currently an Associate Professor at the Department of Computer Science and Engineering, University of North Texas, and the Director of the NanoSystem Design Laboratory (NSDL, http://nsdl.cse.unt.edu). He obtained Ph.D. in Computer Science and Engineering from the University of South Florida in 2003, Masters degree in Systems Science and Automation from the Indian Institute of Science, Bangalore, India in 1999, and Bachelors degree (with Honors) in Electrical Engineering
References (71)
A secure digital camera architecture for integrated real-time digital rights management
J Syst Archit – Embed Syst Des
(2009)- et al.
An efficient double-filter hardware architecture for H.264/AVC deblocking filtering
IEEE Trans Consum Electron
(2008) - Semiconductor Industry Association. International technology roadmap for semiconductors....
- Mohanty SP. Unified challenges in nano-CMOS high-level synthesis. In: Proceedings of the international conference on...
- Chantem T, Dick RP, Hu XS. Temperature-aware scheduling and assignment for hard real-time applications on MPSoCs. In:...
- et al.
High-performance CMOS variability in the 65-nm regime and beyond
IBM J Res Dev
(2006) - et al.
Low-power high-level synthesis for nanoscale CMOS circuits
(2008) - Hansen JG. Design of CMOS cell libraries for minimal leakage currents. Master’s thesis. Dept. of Informatics and...
- Tiri K, Schaumont P, Verbauwhede I. Side-channel leakage tolerant architectures. In: Proceedings of the third...
- et al.
A watermarking co-processor for new generation graphics processing units
Routing for manufacturability and reliability
IEEE Circ Syst Mag
Understanding MOSFET mismatch for analog design
IEEE J Solid-State Circ
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Proc IEEE
Simultaneous peak and average power minimization during datapath scheduling
IEEE Trans Circ Syst I: Regular Papers
A minimum total power methodology for projecting limits of CMOS GSI
IEEE Trans VLSI Syst
A circuit-level perspective of the optimum gate oxide thickness
IEEE Trans Electron Dev
Optimal design of a dual-oxide nano-CMOS universal level converter for multi- SoCs
Analog Integr Circ Signal Proces
Optimizing power using transformations
IEEE Trans Comput-Aided Des Integr Circ Syst
Energy efficient datapath scheduling using multiple voltages and dynamic clocking
ACM Trans Des Autom Electron Syst (TODAES)
Power optimization with power islands synthesis
IEEE Trans Comput-Aided Des Integr Circ Syst
Gate oxide leakage current analysis and reduction for VLSI circuits
IEEE Trans VLSI Syst
Low-power design using multiple channel lengths and oxide thicknesses
IEEE Des Test Comput
Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits
IEEE Trans VLSI Syst
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Saraju P. Mohanty is currently an Associate Professor at the Department of Computer Science and Engineering, University of North Texas, and the Director of the NanoSystem Design Laboratory (NSDL, http://nsdl.cse.unt.edu). He obtained Ph.D. in Computer Science and Engineering from the University of South Florida in 2003, Masters degree in Systems Science and Automation from the Indian Institute of Science, Bangalore, India in 1999, and Bachelors degree (with Honors) in Electrical Engineering from Orissa University of Agriculture and Technology, Bhubaneswar, India in 1995. His research interest is in “Low-Power High-Performance Nanoelectronics”. His research is funded by National Science Foundation and Semiconductor Research Corporation. He is an author of 160+ peer-reviewed journal and conference publications, and 2 books. The publications are well-received by the world-wide peers with a total of 1600+ citations leading to an H-index of 21 and i10-index of 46 (from Google Scholar). He is an inventor of 2 US patents. He has supervised 24 dissertations (Ph.D.) and theses (Masters) and the students are well-placed in industry and academia. He has received recognition as an inspirational faculty at UNT for the years 2008, 2009, 2011, and 2012. He serves on the organizing/program committee of several international conferences and editorial board of several international journals. He is a senior member of IEEE and ACM. He has served as a guest editor for many prestigious journals including ACM Journal on Emerging Technologies in Computing Systems (JETC) for an issue titled “New Circuit and Architecture Level Solutions for Multidiscipline Systems”, August 2012, and IET Circuits, Devices & Systems (CDS) for an issue titled “Design Methodologies for Nanoelectronic Digital and Analog Circuits”, September 2013. He was a general chair for IEEE-CS Symposium on VLSI (ISVLSI) 2012.
Mahadevan Gomathisankaran is an Assistant Professor in Computer Science and Engineering at the University of North Texas. He received his Ph.D. degree in Computer Engineering from Iowa State University. He is the recipient of IBM Ph.D. Fellowship award for the academic years 2004 and 2005. Mahadevan is interested in building secure computing systems. Towards that goal he has designed various cryptographic functions that achieve the required security with minimal circuit complexity, proposed new secure processor architecture that root the security in the hardware, and designed a testing framework that can test the security of the systems. He has published more than 20 articles in leading journals and conferences. He is an Associate Editor for the journal “Information Systems Security: A Global Perspective”. He has served in technical program committees of several international conferences.
Elias Kougianos is currently an Associate Professor in the Department of Engineering Technology, at the University of North Texas (UNT), Denton, TX. He received a BSEE from the University of Patras, Greece in 1985 and an M.S. (EE) in 1987, an M.S. in Physics in 1988 and a Ph.D. in EE in 1997, all from Lousiana State University. From 1988 through 1997 he was with Texas Instruments, Inc., in Houston and Dallas, TX. Initially he concentrated on process integration of flash memories and later as a researcher in the areas of Technology CAD and VLSI CAD development. In 1997 he joined Avant! Corp. (now Synopsys) in Phoenix, AZ as a Senior Applications engineer and in 2001 he joined Cadence Design Systems, Inc., in Dallas, TX as a Senior Architect in Analog/Mixed-Signal Custom IC design. He has been at UNT since 2004. His research interests are in the area of Analog/Mixed-Signal/RF IC design and simulation and in the development of VLSI architectures for multimedia applications. He is author or co-author of over 90 peer-reviewed journal and conference publications. He is a senior member of IEEE.
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Reviews processed and approved for publication by Editor-in-Chief Dr. Manu Malek.
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http://nsdl.cse.unt.edu.
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http://tssl.cse.unt.edu/.