A system on chip for automatic karyotyping system

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Abstract

The Automatic karyotyping System is a computer-aided tool that automates the chromosome analysis and karyotyping processes, manually performed in most cytogenetic laboratories. Artificial neural networks (ANNs) have been widely used in chromosome classification due to their parallelism that reduces the computational complexity and time. However, existing classifiers are software-based, running on a computer that transforms the parallelism features of the ANNs into serial operations, thus significantly reducing their computing power. To efficiently address the above issue due to software implementation, we propose a Field-Programmable Gate Array-based System on Chip (SoC) architecture for human chromosome classification. The hardware implementation of such system can achieve the parallelism inherent to ANNs while reducing the power consumption and circuit size, thus the cost of designing such a system is reduced. The achieved part concerns the classification subsystem based on Kohonen neural network, which has been successfully tested on FPGA platform.

Introduction

The correlation between human diseases and chromosome abnormalities has been recognized since 1956, when Tjio and Levan [1] discovered that the number of human chromosomes was 46. Thus, chromosome analysis and karyotyping (a standard representation of the 23 pairs of chromosomes) are becoming key procedures for efficient genetic diseases diagnosis. However, traditional chromosome karyotyping processes are performed manually in most cytogenetic laboratories. In fact, the cytogeneticist must cut the individual chromosomes in the metaphase images (where the chromosomes appear as a succession of dark and light bands) and visually determine their centromere location in order to evaluate the arm length of each chromosome. The chromosomes of each class are paired and pasted together in decreasing order of size in the karyotype. The preliminary ordering is by length and centromere position for numerical abnormalities detection. Furthermore, additional time and effort are needed for structural abnormalities detection; in this case the cytogeneticist should revise the resulting karyotype according to the banding patterns (typically 400–800 visible bands).

The steps of centromere location, chromosome isolation, chromosome arm length evaluation, chromosome counting, banding observation, and pairing are performed manually. All these procedures require meticulous attention to details, which makes the process of manual karyotype repetitive and time-consuming. Computer-aided systems for chromosome classification are therefore highly needed to automate the chromosome analysis and help cytogeneticists to efficiently perform this time-consuming task.

Various computer-aided systems [2], [3], [4], [5], [6] have been developed to automate the chromosome classification procedure and karyotype establishment routine as well as the chromosomes abnormalities detection. Artificial neural networks have been widely adopted for chromosome classification, due to their processing capacity inherent to their parallel architectures. However, most of the works done in this area consist of software implementations running on a conventional computer that transforms the parallelism features of the ANNs to serial operations, thus reducing their computing power. On the other hand, commercially available automated systems for karyotyping are semi-automatic and still expensive [5], [7].

To the best of the authors’ knowledge, there are no hardware implementations for chromosome classification systems in the available literature; existing Automatic Karyotyping Systems (AKS) are software-based. Since a hardware implementation of such system can recreate the parallelism inherent to neural networks, we designed a system on chip for human chromosome classification, while reducing power consumption, circuit size, and the design cost.

Fully parallel modules can be achieved by Application Specific Integrated Circuits (ASICs) and Very-Large-Scale Integration (VLSI) circuits but it is expensive and time consuming to design such chips. We therefore targeted a Field-Programmable Gate Array (FPGA) platform to validate the functionality of the proposed architecture. This choice is justified by its processing capabilities and relatively reduced development cycle and cost. Also, the proposed architectural model is technology-independent and can be implemented on another technology. FPGA-based implementation of ANN, mainly for classification applications, allows parallelism and easy storage of input data and the synaptic weights. The motivations behind an FPGA-based SoC for automatic chromosome classification are mainly:

  • 1.

    Parallelism: The software-based implementation of these systems running on a conventional computer transforms the parallelism features of the ANN into serial operations. Because the FPGA combines parallel computing, function integration of the system and low power dissipation, the hardware implementation of such system can achieve the parallelism required by ANN and significantly increase its speed.

  • 2.

    Reduced processing time: One major improvement with the hardware implementation of such chromosomes classifier is in the training processing time, i.e., in the enhancement of the convergence time, which is an important issue. The network convergence time of software-based ANN classifiers is in the range of 20 s–50 s, whereas the convergence time of the proposed hardware ANN classifier is about 409 µs.

  • 3.

    Reduced power consumption: FPGA-based SoC for human chromosome classification is indeed less power consuming than a software-based one.

  • 4.

    Miniaturization: The SoC based on FPGA implementation allows a miniaturization of the chromosomes classifier thus, considerably reducing the space used by conventional computers or any related equipment.

This paper is organized as follows: In Section 2 we present a state-of-art-of ANN-based chromosome classification systems and feature extraction techniques. The Kohonen self-organizing map neural network is described in Section 3. An insight into the adopted methodology for the SoC-AKS elaboration is given in Section 4. Section 5 describes the proposed hardware architecture, mainly the Kohonen ANN-based classifier. The system prototyping results are exposed in Section 6. Finally, discussions and conclusions are given in Section 7 and Section 8, respectively.

Section snippets

Related works

This section undertakes a review of previous works related to ANN-based classifiers and feature extraction methods. Various ANN models have been used for the chromosome classification [8], mainly the Multi-Layer Perceptron (MLP) [4], [9], [10], [11], [12]. For example, in [12], Eskiizmirliler et al. proposed a hybrid structure that combines a supervised ANN (MLP) for numerical abnormalities detection and unsupervised ANN (Kohonen) for structural abnormalities detection. Besides the MLP,

Kohonen self-organizing map neural network

The Kohonen self-organizing map (SOM) neural network proposed by Kohonen [23] is an unsupervised competitive learning network. It organizes itself during the learning process; the neurons are organized, usually in a one-dimensional or bi-dimensional network. Fig. 1 illustrates a bi-dimensional network in a square topology; this latter is the commonly used topology. The first layer contains the patterns to be presented to the output layer, which contains neurons that compete among themselves to

Methodology

This section discusses the adopted methodology to elaborate a system on chip for automatic chromosome classification. The aim is to improve the system performance by exploiting the processing capabilities of reconfigurable architectures such as the FPGA devices.

SoC-AKS architecture presentation

The hardware implementation of the proposed system consists of three main building blocks (Fig. 3). In this work, we focus mainly on the achieved part of the SoC-AKS, i.e., the classification subsystem; the other subsystems are not within the scope of this paper.

The system uses the USB controller to acquire data from the USB microscope, a digital microscope that integrates a sensor/camera and can be connected to the FPGA/SoC via the USB interface chip (A Cypress CY7C67300) of the ML501

System prototyping

Due to the SoC complexity, we designed and implemented the subsystems separately. We started by designing the classification subsystem, which is the main part of the SoC-AKS. This subsystem, based on a combination of Kohonen neural networks, is first prototyped using the Xilinx Spartan3E development platform for functional validation. Since the SoC-AKS includes other subsystems and the Spartan3E resources are limited; an investigation was performed to select the most suitable FPGA family that

Discussions

To evaluate the performance of the proposed classifier, 130 features (128 DPs + CI + L) were used. The results show that the geometrical features (L, CI) give a better recognition rate when used separately, compared to the density profile. We have also noticed that the combination of the features (DP + CI + L) gives a maximum recognition rate, which is about 65.5%; this rate is acceptable and similar to that obtained with software implementations.

Table 4 gives a comparison of the proposed

Conclusion

In this work, an efficient hardware implementation of an AKS is proposed, the aim being to improve the performance of the system by exploiting the parallelism inherent to ANNs. For the first time, an architectural model for the SoC-AKS was successfully implemented on a platform, which allows parallel execution, portability, low power consumption, miniaturization, and reduced computation time vs. software-based classifiers running on PCs.

Promising results were obtained regarding the

Faroudja Abid received the engineering degree in electronics engineering from the university of Tizi-ouzou, Algeria; and the M.Sc. from Ecole Nationale Polytechnique (ENP) of Algiers, Algeria. She is now pursuing a Ph.D. degree at the electronics department, ENP. Currently, she is a researcher at CDTA center. Her research interests include embedded system, FPGA and ASIC design, System on Chip and neural network.

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  • Faroudja Abid received the engineering degree in electronics engineering from the university of Tizi-ouzou, Algeria; and the M.Sc. from Ecole Nationale Polytechnique (ENP) of Algiers, Algeria. She is now pursuing a Ph.D. degree at the electronics department, ENP. Currently, she is a researcher at CDTA center. Her research interests include embedded system, FPGA and ASIC design, System on Chip and neural network.

    Latifa Hamami (M.Sc. 1988, Ph.D. 2002) is a full professor in the department of electronics at Ecole Nationale Polytechnique (ENP) of Algiers, Algeria. She is a head of the Signal and Communications laboratory and the image processing and pattern recognition team. She authors more than 100 scientific papers. Her research interests include medical image processing, optical character recognition and biometrics.

    Faiza Badache received the engineering degree in electronics engineering from the Ecole Nationale Polytechnique (ENP) of Algiers, Algeria in 2011; and the Master's degree in electronic instrumentation from the University of Sciences and Technology Houari Boumedienne (USTHB) of Algiers, Algeria in 2016. She was with the Signal and Communication laboratory in 2011.

    Houssem Derdour received the engineering degree in electronics engineering from the Ecole Nationale Polytechnique (ENP) of Algiers, Algeria. He was with the Signal and Communication laboratory in 2011.

    Reviews processed and recommended for publication to the Editor-in-Chief by Associate Editor Dr. A. Isazadeh.

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