Low-complexity implementation of efficient reconfigurable structure for cost-effective hearing aids using fractional interpolation

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Abstract

Digital hearing aids can be made less expensive if they are reconfigurable and of low hardware complexity. Hence, this work proposes a hardware-efficient, reconfigurable filter bank structure, based on fractional interpolation. The proposed structure is reconfigurable since a single structure can be used for different patients with different types of hearing impairments. The proposed structure consists of a masking stage and a scheme generation stage with a prototype filter in each stage. The prototype filters are made multiplier-less by representing their coefficients in the CSD space. The filter characteristics are improved by deploying a MOABC optimization algorithm. The number of adders is reduced using the SIDC-CSE technique. The low-complexity structure can be used for all types of hearing impairments, with the matching error and delay within tolerable ranges. The proposed structure has been implemented on an FPGA to support the analytical results for low hardware complexity and hence low power.

Introduction

Digital hearing aids help to compensate for the hearing loss of a hearing-impaired person. In a hearing aid, sounds at all frequencies are amplified selectively and are transmitted to the ear. A block diagram of a digital hearing aid [1] is illustrated in Fig. 1. The analogue output of the microphone is digitized by an analogue-to-digital converter, shown as A/D, which is fed as the input to the filter bank. The filter bank block, consisting of a bank of filters and gain blocks, is a vital part of a digital hearing aid. The input signal is broken down into various sub-band components by the bank of filters. The gain block provides selective amplification to each of these sub-bands, according to the person’s hearing ability. These sub-bands are additively combined, and then converted back into an analogue signal by a digital-to-analogue converter labeled as D/A in Fig. 1.

An audiogram is a graph which represents a person’s hearing ability at different frequencies. A typical audiogram along with the necessary details of the hearing levels is shown in Fig. 2. A person’s hearing level at different frequencies can be determined from the audiogram. According to the intensity values, hearing loss is categorized as normal (0 to 20 dB), mild (20 to 40 dB), moderate (40 to 70 dB), severe (70 to 90 dB) or profound (greater than 90 dB) [2]. Intensity measures are obtained for an audiogram at different frequencies ranging from 125 Hz to 8000 Hz. The audiogram shown in Fig. 2 corresponds to a person suffering from noise exposure [3]. The matching error, which is the difference between the hearing loss curve and the matching curve, measures the quality of the filter design.  ±  3 dB is reported as the tolerable matching error [4], [5].

There are various articles in the literature that discuss the different approaches to designing the digital filter bank block in a hearing aid. A variable bandwidth filter bank with sub-band generation technique is discussed in [6], where the sample-rate conversion technique is utilized. However, this method results in a structure with a higher hardware complexity compared to that used in [7], [8]. In [7], [8], the farrow structure is adopted to generate the sub-bands with non-uniform bandwidths using variable bandwidth filters.

In [9], the frequency response masking (FRM) filter technique is used to generate the non-uniform sub-bands. However, the matching error is above the acceptable range of  ±  3 dB. The inaccuracy due to the high matching error in [9] is reduced in [10], using cosine modulated filter banks (CMFBs) with non-uniform sub-bands. For the majority of the audiogram matching methods in the literature using digital filter structures, the filter count is equal to the number of non-uniform/uniform sub-bands that are needed to cover the whole frequency range. This results in high hardware complexity. However, matching errors within an acceptable range are achieved by the structure proposed in [11] along with low hardware complexity. A major drawback of this structure, is the processing delay, which exceeds the tolerable value of 20 ms [12]. This problem is rectified in [13] using a modified structure employing fractional interpolation. This utilizes only two filters, thereby reducing the hardware complexity. However, this structure imposes a limit on the number of sub-bands that are generated, which in turn, restricts the flexibility to match a variety of audiograms. A greater number of audiograms are matched using the structure proposed by the authors in [14]. However, the disadvantage of the structure in [14] is that the device utilization of this structure is greater and the delay in some cases exceeds the maximum tolerable value of 20 ms [12].

Non-uniform sub-bands for the hearing aids, are generated in [15], taking non-linear transformation on the uniform sub-bands, obtained by performing the cosine modulated technique on a prototype filter. This structure is reconfigurable with low complexity and delay. However, the matching error for some audiograms is greater than  ±  3 dB and the hardware complexity is higher than that in [13].

In this paper, the structure in [13] is modified in such a way as to overcome its major disadvantage, i.e. a modified structure is proposed which is used to reduce the matching error for all types of hearing impairments and can be used to match a variety of audiograms. The hardware complexity is also lower than that of all existing structures. In the proposed structure, the generation of the sub-bands is carried out in two stages. The masking stage forms the first stage, which divides the entire range of frequencies into three uniform regions, and the second stage, the scheme generation stage, comprises two levels for generating a greater number of sub-bands. The sub-bands generated in the different levels can be selected with the help of control signals. There are two prototype filters in the proposed structure. One prototype filter is used in the masking stage to generate three uniform regions and the other is used in the scheme generation stage to generate the sub-bands. In the proposed filter bank structure, different sub-bands are generated using a 7-bit control signal without changing the structure of the filter bank. Hence, the proposed structure is reconfigurable and can help the audiologist to customize the hearing aid, based on the patient’s level of hearing loss. Low matching error and delay can be achieved using the proposed structure with low hardware complexity for all types of audiograms.

This paper also focuses on designing the two prototype filters used in the proposed structure in such a way as to achieve very low hardware complexity. This is done by first representing the continuous coefficients in the canonic signed digit (CSD) space. The filter is then made totally multiplier-less, which results in only adders and shifters. However, this can lead to the degradation of the filter characteristics. Hence a multi-objective optimization technique such as a multi-objective Artificial Bee Colony (MOABC) algorithm is deployed in the integer space in order to obtain the optimized coefficients which lead to better filter characteristics with fewer adders. The number of adders is drastically reduced by using a low-complexity implementation technique for the filter, using a minimal spanning tree approach [16]. This approach uses shift inclusive differential coefficients (SIDCs) with common sub-expression elimination (CSE). This results in a minimal number of adders, which leads to a small chip area and power dissipation. Hardware implementation is also carried out and the results are presented.

Table 1 shows, the symbols used in this paper.

The paper is structured as follows. An overview of the fractional interpolation filter is given in Section 2. The proposed filter bank structure is described in Section 3. Section 4 illustrates the multiplier-less prototype filter design for the proposed filter bank structure. Section 5 provides the results obtained using the proposed structure for hearing aid application. Finally, Section 6 describes the conclusion.

Section snippets

Theoretical framework for the design of the proposed structure

Fractional interpolation [13], [17] is the basic idea used in this paper to create the sub-bands in the proposed filter bank structure.A reconfigurable structure can be realized using the fractional interpolation technique. Let the frequency responses of a prototype filter and its fractional interpolated version be represented as G(z) and G(zM/D), respectively, where M is the interpolation factor and D is the decimation factor. The fractional interpolation changes the sampling rate by a factor

The proposed filter bank structure

The proposed fractional interpolation-based hardware-efficient filter bank structure for digital hearing aids is shown in Fig. 5. The masking block and scheme generation block are the two stages of this structure. The working of the two stages is explained in Sections 3.1 and 3.2, respectively.

The proposed structure with multiplier-less prototype filters

Reducing the size and cost of the hearing aid is a challenge, taking into account the increasing number of patients with hearing impairements.

Multipliers are the most power-and space-consuming components in any filter. Hence, the two prototype filters in the proposed structure, i.e. F(z) and H(z), are made totally multiplier-less, with the least number of adders. To this end, the CSD representation of the coefficients, the MOABC optimization and SIDC’s with CSE are deployed [16].

Results

The structure proposed in this paper is used for audiogram matching. The prototype FIR linear phase filters F(z) and H(z) in the structure in Fig. 5 are designed with the following specifications, as given in [13], using the Parks McClellan algorithm.

H(z):

  • Normalized passband frequency = 0.16 π

  • Normalized stopband frequency = 0.3 π

  • Passband ripple = 0.0065 dB

  • Stopband attenuation = −66.5 dB

F(z):

  • Normalized passband frequency = 0.3π

  • Normalized stopband frequency = 0.3667π

  • Passband ripple = 0.035 dB

Conclusion

This work proposes a reconfigurable filter bank structure based on fractional interpolation. The structure has two stages, with one prototype filter in each stage. The multipliers in the prototype filters are expensive since they occupy a greater area and may lead to high power dissipation. In the proposed filter bank structure, the multipliers of the prototype filters of the two stages are converted to adders and shifters using the canonic signed digit representation. The filter

Amir A. received his BTech degree in Electronics and Communication Engineering from the College of Engineering Adoor, India, in 2010, his MTech in Communication Engineering from VIT University, India, in 2013 and his Ph.D from the National Institute of Technology Calicut, India, in 2018. He is currently Assistant Professor in the Department of Electronics and Communication Engineering, Acharya Institute of Technology, India. His research areas are digital signal processing, filter design,

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  • Cited by (11)

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    Amir A. received his BTech degree in Electronics and Communication Engineering from the College of Engineering Adoor, India, in 2010, his MTech in Communication Engineering from VIT University, India, in 2013 and his Ph.D from the National Institute of Technology Calicut, India, in 2018. He is currently Assistant Professor in the Department of Electronics and Communication Engineering, Acharya Institute of Technology, India. His research areas are digital signal processing, filter design, multi-rate filter banks and machine learning.

    Bindiya T. S. received her BTech from Model Engineering College, Ernakulam, India, in 2004, her MTech from Amrita Vishwa Vidyapeetham, Coimbatore, India, in 2006 and her Ph.D from the National Institute of Technology Calicut, India, in 2014. She is currently Assistant Professor in the Department of Electronics and Communication Engineering, National Institute of Techology Calicut. Her research interests include digital signal processing, multi-rate signal processing and digital VLSI circuits.

    Elizabeth Elias received her B.Sc Eng. and M.Sc Eng. from the College of Engineering, Trivandrum, India, in 1975 and 1978, respectively, and her PhD from the Indian Institute of Technology, Madras, India, in 1989. She completed one year of post-doctoral research at Linko¨ping University, Sweden, in 2001. Prior to her retirement, she was a Professor in the Department of Electronics and Communication Engineering at the National Institute of Techology Calicut. Her research interests include digital signal processing, digital filter design and multi-rate signal processing.

    Reviews processed and recommended for publication to the Editor-in-Chief by Area Editor Dr. E. Cabal-Yepez.

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