Efficient hardware architecture of 2D-scan-based wavelet watermarking for image and video

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Abstract

This paper describes an efficient hardware architecture of 2D-Scan-based-Wavelet watermarking for image and video. The potential application for this architecture includes broadcast monitoring of video sequences for High Definition Television (HDTV) and DVD protection and access control. The proposed 2D design allows even distribution of the processing load onto a set of filters, with each set performing the calculation for one dimension according to the scan-based process. The video protection is achieved by the insertion of watermarks bank within the middle frequency of wavelet coefficients related to video frames by their selective quantization. The 2-D DWT is applied for both video stream and watermark in order to make the watermarking scheme robust and perceptually invisible. The proposed architecture has a very simple control part, since the data are operated in a row-column-slice fashion. This organization reduces the requirement of on-chip memory. In addition, the control unit selects which coefficient to pass to the low-pass and high-pass filters. The on-chip memory will be small as compared to the input size since it depends solely on the filter sizes. Due to the pipelining, all filters are utilized for 100% of the time except during the start-up and wind-down times. The major contribution of this research is towards the selection of appropriate real time watermarking scheme and performing a trade-off between the algorithmic aspects of our proposed watermarking scheme and the hardware implementation technique. The hardware architecture is designed, as a watermarking based IP core with the Avalon interface related to NIOS embedded processor, and tested in order to evaluate the performance of our proposed watermarking algorithm. This architecture has been implemented on the Altera Stratix-II Field Programmable Gate Array (FPGA) prototyping board. Experimental results are presented to demonstrate the capability of the proposed watermarking system for real time applications and its robustness against malicious attacks.

Introduction

The recent advancement in digital multimedia technology has made it possible to transmit more and more digital multimedia signals through the network. This development leads to protecting the copyright and identifying the ownership of all documents using the digital watermarking technology. It is accomplished by embedding the authentication data in the digital media in an efficient and secure way. Once the watermark is inserted in the image, it must be too difficult to be removed. For copyright protection purpose, an image watermarking scheme should be robust against common signal processing and attacks.

With regard to the domain where the watermark embedding occurs, we can distinguish methods operating in the spatial domain [1], [2], [3] and transform-domain (Discrete Cosine Transform (DCT), Discrete Fourier Transform (DFT) and Discrete Wavelet Transform (DWT), Wavelet, etc.) embedding [4], [5]. When considering a watermarking scheme, depending on its specific application, different requirements need to be achieved. For example, in most of the video coding standards (such as H.261, MPEG-1, MPEG-2 and MPEG-4), the hybrid motion compensation/discrete cosine transform (MC/DCT) coding method is commonly used. So, the watermarking technique is performed in the DCT domain where the watermark can be embedded into the intra-frame or into the non-intra-frame according to the type of implementation [6], [7]. In addition, in UMTS applications, MPEG-2 coded video sequences can be potentially distributed to mobile terminals requiring copyright protection, authenticity verification. These features are achieved by digital watermarking using spread spectrum approach based on DCT transform also [8]. Recently, JPEG2000 has emerged as the new standard for still image compression because of its superior efficiency. It supports both lossy and lossless compressions. For the lossless part, the 5/3 wavelet filter is used. So, for image watermarking, data are embedded into the DWT domain [9], [10]. Most of these solutions are implemented in software where focusing on the algorithmic aspect.

The multi-resolution technique based on the wavelet transform [11], [12], [13], [14] has attracted much attention in the recent years because it gives a spatial/frequential vision, which optimize the insertion and brings a high security against attacks. In the proposed system it is impossible for a would-be-pirate to know which specific wavelet domain has been used for embedding. In our decomposition, we have used 3 levels in this paper.

The rest of the paper is organized as follows. Section 2 highlights the contribution of this paper after discussing the earlier watermarking techniques and the few hardware-based watermarking systems mentioned in the current literature. Section 3 discusses and explains the proposed watermarking scheme in detail and addresses architectural features to offer a certain degree of robustness to attacks. Section 4 presents the real-time FPGA-based hardware implementation issues for the proposed watermarking scheme. The subsequent sections, 5 Hardware implementation results, 6 Conclusion, discuss the experimental results and conclusions, respectively.

Section snippets

Previous work

The importance of digital content authentication has made the development of many watermarking scheme to address the ownership protection for image, video, audio and text data. The algorithms work in various domains like spatial, DCT, and wavelet and insert-extract different types of watermarks including invisible robust, invisible fragile, and visible. Watermarking techniques that embed hidden information in the spatial domain, such as [15], [16], [17] are definitely more straightforward and

The watermarking scheme

Our proposed scheme is based on the 2D-Scan based Pyramid Wavelet watermarking. We have chosen the transform domain because it allows a high degree of robustness against attacks voluntary or not. Even the watermarking techniques using the 2D-DWT need an expensive computation, we have developed a special insertion technique combined with a scan based one to optimize the hardware implementation in order to be convenient for video data. In addition, we have used a quantization process in order to

Watermarking system architecture

The proposed watermarking technique presented before as hardware architecture needs a judicious cutting out with respect to temporal constraints of the video flow and keep the hardware size small. We have designed the watermarking architecture exploiting a high degree of parallelism, pipeline and re-using (see Fig. 4) by integrating:

  • Three separate stage to compute the three levels of 2D-DWT direct and reverse.

  • Six insertion blocks related to the corresponding six sub-bands to be watermarked

  • The

Hardware implementation results

In this section, we present the design results of the proposed watermarking architecture in terms of temporal distribution for all hardware components and complexity involved in the generation of the RTL architecture, visual quality of the watermarked video stream and the end-to-end processing delay. We followed a top-down modular design approach in performing the architectural design, simulation and FPGA prototyping. We logically and structurally divided an architectural unit into several

Conclusion

In this paper we have proposed an improved hardware watermarking scheme for images and video frames. This scheme consists of a blind technique based on a 2D-DWT multi-resolution analysis with a scan based computing scheme. Our RTL architecture exploits inherent parallelism and pipelining techniques to suit well with the real time character of the video frames. In addition, after the optimization of the last version, only about 50% of the memory and FPGA resources related to the STRATIX II

Acknowledgements

The authors would like to thank Princess Fatimah Alnijris' Research Chair of Advanced Manufacturing Technology for supporting this research.

Sourour Karmani received his M.S. degree in Microelectronics from the Science Faculty of Monastir, Tunisia, in 2002. Currently, he is a Ph.D. student. His research interests include watermarking of images and video, System on Chip (SoC) Design, IP interfaces, and Performance Evaluation.

Ridha Djemal received his Ph.D. degree in Microelectronics from the Institut National Polytechnique de Grenoble (INPG France) in 1996. Since 2007, he is an Associate Professor in the Electrical Engineering

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  • Sourour Karmani received his M.S. degree in Microelectronics from the Science Faculty of Monastir, Tunisia, in 2002. Currently, he is a Ph.D. student. His research interests include watermarking of images and video, System on Chip (SoC) Design, IP interfaces, and Performance Evaluation.

    Ridha Djemal received his Ph.D. degree in Microelectronics from the Institut National Polytechnique de Grenoble (INPG France) in 1996. Since 2007, he is an Associate Professor in the Electrical Engineering Department at the King Saud University. His research activities concern System Design, image and video processing, Encryption and Communication Network, IP interfaces and Formal Verification for System on Chip (SoC).

    Rached Tourki received his B.S. degree in Physics (Electronics option) from Tunis University in 1970, the M.S. and the Doctorat de 3eme cycle in Electronics from the Institut d’Electronique d’Orsay, Paris-South University in 1971 and 1973, respectively. From 1973 to 1974, he served as Microelectronics Engineer in Thomson-CSF. He received his Doctorat d’Etat in Physics from Nice University in 1979. Since this date, he has been a Professor in Microelectronics and Microprocessors with the Physics Department, Faculté des Sciences de Monastir. His current research interests include digital signal processing and Hardware−Software Codesign for rapid prototyping in telecommunications.

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