Digital estimation and compensation method for nonlinearity mismatches in time-interleaved analog-to-digital converters
Introduction
Along with the increasing requirements on high performance, it becomes more and more difficult to simultaneously satisfy a high sampling rate and a high resolution by utilizing a single analog-to-digital converter (ADC). To address this problem, Black and Hodges proposed a sampling system with multiple, say M, parallel ADCs operating in a circulatory manner, i.e., the time-interleaved ADCs (TIADCs) [1]. This architecture increases the sampling rate by a factor of M. However, the TIADC is sensitive to mismatches between the parallel channels, where a small deviation will result in a serious degradation in the overall TIADC's performance [2], [3]. For high resolution, it is therefore crucial to match the interleaved channels with a high accuracy.
Much effort has been laid on understanding and mitigating the effects of offset, gain, timing, and frequency response mismatches in TIADCs [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18]. Generally, the correction of mismatches can be accomplished either in the foreground (using training signals) or in the background (blind correction). In a foreground setup, a training signal (e.g., a sinusoidal, ramp, or even DC) is used to determine the channel mismatches [4], [11]. Using background calibration, the channel mismatches can be calibrated utilizing the information in the TIADC's output. Most background methods require some assumptions on the input signal (e.g., slight oversampling, wide-sense stationarity, or sparse frequency spectrum) [6], [7], [8], [9], [12], [13], [14]. Nonlinearity mismatches can be introduced by the imperfection of the analog front-end circuits as well as the sub-ADCs. Compared with the typically well-known channel mismatches (i.e., offset, gain, timing, and frequency response mismatches), nonlinearity mismatches will generate additional distortions in the spectrum, which can also greatly degrade the dynamic performance, for example the spurious-free dynamic range (SFDR) of the TIADC, especially in high-resolution applications [19], [20]. Therefore, to further enhance the TIADC's dynamic performance, one needs to consider and calibrate nonlinearity mismatches rather than merely the typical channel mismatches [19]. However, only a few contributions have addressed nonlinearity mismatches in TIADCs [19], [20], [21], [22], [23]. In [21], theoretical expressions for DNL and INL errors were derived, but this mismatch model could not completely characterize the actual interleaved sampling system. In [22], the effects of channel nonlinearity mismatches were analyzed and simulated, but the authors did not give detailed mathematical derivations. In [20] and [23], the authors analyzed the spectrum characteristics of nonlinearity mismatches through a mathematical framework based on hybrid filter banks and developed a compensation method by utilizing a randomization strategy. This strategy however needs additional ADCs, which increases the hardware cost. Some reports address efficient INL estimation algorithms for a single ADC based on polynomial models, where a smooth approximation of the INL is sufficient [24], [25], [26]. However, the spectral-based method did not consider time-interleaved structures. If they are directly adopted for TIADCs, more computing resources would have to be used.
In this work, we propose a calibration method to compensate for polynomial-represented nonlinearity mismatches in TIADCs. The strategy can be divided into two steps: the foreground estimation using a sinusoidal training signal and the digital compensation using a cascaded structure employing multipliers and adders. The contributions are further explained and outlined below:
1) Analysis of Nonlinearity Mismatches: From a high-level perspective, we model the nonlinearity mismatches of an M-channel TIADC by employing Lth-order polynomials. This model is also used in [20] and [23]. Here we extend those results by deriving and simulating the mathematical expression for a quantitative analysis of the influence of nonlinearity mismatches on the signal-to-noise and distortion ratio (SNDR). These results can be used during the design phase of TIADCs to determine the mismatch tolerance as well as the precision requirements for the post estimation and compensation method.
2) Foreground Estimation Method: We propose a foreground estimation method for nonlinearity mismatches, where independent mismatch distortions are firstly determined and then utilized to calculate the polynomial coefficients through the inverse discrete-time Fourier transform (IDTFT). The proposed method can achieve the same accuracy with the spectral-based method by using less computational resources. The detailed complexity comparison is presented in Section 5.5. Compared with [27], we discuss and verify the estimation performance with the coexistence of offset, gain, and time-skew mismatches. Moreover, it is worth noting that if the nonlinearity mismatches are not taken into account, the performance of the spectral-based foreground estimation method for offset and gain mismatches will be influenced by the overlap with nonlinearity mismatch distortions.
3) Digital Compensation Method: We introduce a compensation structure based on cascaded multipliers and adders. This method can directly use the estimated coefficients of the polynomial-represented nonlinearity mismatches. It is evaluated for third-order polynomial nonlinearity mismatches with different types of input signals. Compared with the method using randomization [20], our method can achieve better efficiency by avoiding the use of additional sub-ADCs.
4) Consideration of Practical Issues: To make the method more practical than the previously suggested one [27], we present simulation examples taking practical mismatch levels into account to verify the robustness of the calibration method. The requirement on the training sinusoidal signal is discussed in the paper
In this paper, we consider the nonlinearity mismatches with frequency independence, i.e., the polynomial coefficients are assumed to be independent of the input frequency. The proposed estimation and compensation method is viable and brings substantial performance improvements, when the TIADCs feature frequency-independent nonlinearity characteristics [26], [28], [29], [30], [31]. It is worth noting that Volterra series or Wiener series are required to model the frequency-dependent nonlinearities to achieve further enhancement, especially in ultra-wideband applications. However the computational complexity will substantially increase and may make the performance improvement insufficient compared to the introduced hardware cost [26], [30], [31].
The outline of this paper is as follows. In Section 2, we analyze the characteristics of nonlinearity mismatches. In Section 3, the foreground estimation method is described in detail. In Section 4, we introduce a digital compensation method based on a cascaded structure. In Section 5, behavioral-level simulation results are presented. Section 6 concludes the work.
Section snippets
Characteristics of nonlinearity mismatches
One can either use hybrid filter bank representation or time-varying filter representation to investigate TIADCs. In this paper, it is more convenient to derive the equations and analyze the distortions caused by nonlinearity mismatches by using the hybrid filter bank modelling [32]. As shown in Fig. 1, the system model consists of an analog analysis filter bank, M sub-ADCs, M upsamplers, and a digital synthesis filter bank. The overall sampling rate of the system is , and is the
Foreground estimation method
We propose a foreground estimation method, where a sinusoidal signal is employed as input during the estimation procedure. The purpose of the estimation method is to derive the polynomial coefficients from the TIADC's output spectrum. Therefore, for an M-channel TIADC with Lth-order polynomial nonlinearity mismatches, there is a total of coefficients to be determined.
According to the above derivations, it can be found that is the discrete-time Fourier transform (DTFT) of the
Compensation principle
With Lth-order polynomial nonlinearity mismatches, the TIADC's output sequence can be expressed as where .
From another perspective, the output sequence can be divided into the original input sequence and the error sequence caused by nonlinearity mismatches. Then, where the error sequence is given by where
The principle of the compensation method is to cancel from by
Simulation results
In the following simulations of this section, a four-channel 16-bit TIADC simulation model is developed by using MATLAB to evaluate the proposed estimation and compensation method. We introduce four third-order polynomials () to represent the nonlinearity mismatches. During estimation, a sinusoidal signal is adopted as the training signal, with an input frequency of and an amplitude of 90% of the FSR of the TIADC. The training signal should have a considerably higher dynamic
Conclusions
In this paper, we have presented a digital calibration strategy for polynomial-represented nonlinearity mismatches in TIADCs. A foreground estimation method and a cascaded compensation scheme are proposed and discussed. The performance of the estimation and compensation method has been demonstrated through behavioral-level simulations. We also take some practical problems (e.g., coexistence of other channel mismatches and the input white noise) into account to evaluate the robustness of the
Yinan Wang received the B.S. degrees in communication engineering from the Central South University, Changsha, China, in 2009. He is currently pursuing the doctoral degree at the Department of Circuit and System of National University of Defense Technology, Changsha, China. Since 2014 he is a Visiting Ph.D. at the Department of Electrical Engineering, Linköping University, Sweden. His research interests include high speed sampling systems and mixed-signal processing systems with focus on
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2022, Microelectronics JournalCitation Excerpt :Each sub-channel requires one adder and one multiplier, and all channels share a derivative filter. The SNDR and SFDR of the TI-ADC were analyzed but did not specify the mismatch value in Ref. [32]. [25] studied the SNDR in four-channel TI-ADC with the first-order Taylor approximation.
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2018, AEU - International Journal of Electronics and CommunicationsAn Oversampling-Based Fast Convergent Blind Technique for Gain Mismatch and Timing Skew Error Correction in Time-Interleaved ADCs
2023, Circuits, Systems, and Signal ProcessingA Foreground Mismatch and Memory Harmonic Distortion Calibration Algorithm for TIADC
2023, IEEE Transactions on Circuits and Systems I: Regular PapersCorrelation-Based Calibration for Nonlinearity Mismatches in Dual-Channel TIADCs
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Yinan Wang received the B.S. degrees in communication engineering from the Central South University, Changsha, China, in 2009. He is currently pursuing the doctoral degree at the Department of Circuit and System of National University of Defense Technology, Changsha, China. Since 2014 he is a Visiting Ph.D. at the Department of Electrical Engineering, Linköping University, Sweden. His research interests include high speed sampling systems and mixed-signal processing systems with focus on digital calibration techniques for time-interleaved analog-to-digital converters and digital enhancing techniques for sampling systems.
Hui Xu received the Ph.D. degree in information engineering from the National University of Defense Technology, Changsha, China, in 1995. He is a Professor in the College of Electrical Science and Engineering, National University of Defense Technology, Changsha, China. His research interests include circuits and signal processing systems. He is a senior member of Chinese Institution of Electronics.
Håkan Johansson received the Master of Science degree in computer science and the Licentiate, Doctoral, and Docent degrees in Electronics Systems from Linköping University, Sweden, in 1995, 1997, 1998, and 2001, respectively. During 1998 and 1999 he held a post doctoral position at Signal Processing Laboratory, Tampere University of Technology, Finland. He is currently Professor in Electronics Systems at the Department of Electrical Engineering of Linköping University. Prof. Johansson's research encompasses theory, design, and implementation of efficient and flexible signal processing systems for various purposes. He is one of the founders of the company Signal Processing Devices Sweden AB that sells advanced signal processing solutions. Prof. Johansson is the author or co-author of 4 books and some 170 international journal and conference papers. He is the co-author of three papers that have received best paper awards and he has authored two invited papers in IEEE Transactions and four invited chapters. Prof. Johansson has served as Associate Editor for IEEE Trans. on Circuits and Systems I and II, IEEE Trans. Signal Processing, and IEEE Signal Processing Letters. He is currently Associate Editor of IEEE Trans. on Circuits and Systems I and Area Editor of the Elsevier Digital Signal Processing journal, and a member of the IEEE Int. Symp. Circuits. Syst. DSP track committee.
Zhaolin Sun received the Ph.D. degree in information engineering from the National University of Defense Technology, Changsha, China, in 2006. He is an Associate Professor in the College of Electronic Science and Engineering, National University of Defense Technology, Changsha, China. His interests include digital signal processing and solid-state storage systems.
J. Jacob Wikner received the Ph.D. degree from the Department of Electrical Engineering, Linköping University, Sweden, in 2001. He has worked as a Research Engineer with Ericsson Microelectronics, as a Senior Analog Design Engineer with Infineon Technologies, and as a Senior Design Engineer and Chip Architect with Sicon Semiconductor. He has been an Associate Professor with Linköping University since 2009. He holds six patents, has published 40 scientific papers, and has co-authored CMOS Data Converters for Telecommunication. He is the cofounder of CogniCatus and AnaCatum Design AB. His current research interests include biologically inspired architectures, high-speed A/D and D/A converters, and general analog and mixed-signal designs.