Elsevier

Digital Signal Processing

Volume 51, April 2016, Pages 82-91
Digital Signal Processing

Unified low-complexity decision feedback equalizer with adjustable double radius constraint

https://doi.org/10.1016/j.dsp.2016.01.012Get rights and content

Abstract

The maximum likelihood sequence estimation (MLSE) is an optimal equalization method to suppress Inter-Symbol Interference (ISI) in communication and storage systems. The Viterbi Algorithm (VA) provides an exact solution of MLSE. To reduce the complexity of VA, MLSE-DFE, which combines the VA within a decision feedback equalizer (DFE), is widely used in practical designs; however, the computing complexity is still too high. In this paper, we propose the SDVA-DFE, a unified DFE combining the concept of sphere detector (SD) and VA. The computing complexity of the SDVA-DFE can be reduced by proposed double radius constraints, upper radius (UR) and lower radius (LR). By adjusting the values of the two radiuses, the SDVA-DFE also provides a trade-off between performance and complexity. Simulation shows that this method is suitable for high-order modulation and long-length channel impulse response. When applied to a Lorentzian channel and channels of different eigenvalue spread, the SDVA-algorithm can reduce the complexity by over 90% at high SNR compared with MLSE-DFE.

Introduction

The maximum likelihood sequence estimation (MLSE), implemented via Viterbi Algorithm (VA) [1], [2], [3], is an optimal equalization method to solve the ISI problem [4], as shown in Fig. 1(a). However, the computing complexity of VA is proportional to the size of the signal set and grows exponentially with the length of channel memories. Many researchers [5], [6], [7], [8] have aimed at low complexity and high performance design compared with MLSE. Recently, Jie Luo [9] mixed the sphere-constrained to Viterbi algorithm for convolutional decoder. Vikalo, et al. [10] proposed a similar idea for ISI channel, which reduces the computing complexity via sphere decoding (SD) algorithm [11], [12], as shown in Fig. 1(b). This method achieves optimal performance with short-length inputs, but fails in the case of continuous inputs. In other words, this equalizer is not a practical design.

In contrast, the decision feedback equalizer (DFE) provides low-complexity approaches [13], [14], [15]. Hence, to further reduce the computing complexity of VA, MLSE-DFE [16], [17] combined decision-feedback (DF) methods with Viterbi algorithm. This technique is also known as the decision-feedback sequence estimator (DFSE) [6]. Fig. 1(c) reveals that the MLSE-DFE uses the MLSE detector instead of a slicer in a normal DFE. In addition, the feedforward filter (FFF) is used as a whitening matched filter (WMF) [18] and the feedback filter (FBF) words as the decision-feedback to merge the data paths from VA earlier. The performance is much better than normal DFE, and the computing complexity of VA is significantly reduced. Hence, this structure is widely used in practical designs. However, the main drawback is that the complexity grows exponentially with the lengths of channel memories.

In addition, many researches [19], [20], [21], [22], [23], [24], [25] have demonstrated many complexity reduction approaches. Soft-Threshold-Based Multilayer Decision Feedback Equalizer (STM-DFE) [26] defines a reliable region (RR) to DFE. As shown in Fig. 1(d), when the DFE output is not in the reliable region, the decision is not made instantly. Instead, the log-likelihood ratio (LLR) is fed to FBF, and the process is repeated continually until the DFE output becomes reliable. As a result, the computing complexity is reduced, but the performance is sacrificed. More importantly, the reliable region is difficult to be designed at high-stage STM-DFE.

As discussed before, three approaches can be used to achieve low computing complexity: (1) removing impossible data paths (SD algorithm) (2) merging residual data paths (DF, DFSE or MLSE-DFE), and (3) selecting the best reliable data paths (RR, STM-DFE). Table 1 summarizes the pros and cons of previous works. Also, the architectures of these works are different. In this paper, we propose the sphere detection-Viterbi algorithm in DFE (SDVA-DFE) that can unify the three approaches. Our proposed system, shown in Fig. 2(a), is comprised of the three techniques as follows:

  • 1)

    Double radius algorithm/constraints: In Fig. 2(a), the radius controller provides double radius constraints to the detector. These radius constraints are the upper and lower radiuses, denoted by dU and dL respectively. As shown in Fig. 2(b), the upper radius, with a function similar to the SD algorithm, restricts the searching algorithm to only search the lattice points lying within it. On the other hand, the lower radius, similar to the RR technique, early terminates the searching algorithm when any lattice point lies within it. Hence, the proposed radius constraints aim to reduce the computing complexity by restricting the search region.

  • 2)

    Combining double sphere constraints with Viterbi algorithm (SDVA) in DFE: We develop the SDVA-algorithm to achieve the maximum likelihood solution. Fig. 2(c) presents the implementation of SDVA detector based on the Viterbi trellis structure with decision-feedback, which merges the residual data paths earlier. As we control the new trellis implementation via double sphere constraints, the proposed algorithm unifies the three approaches in a single structure and considerably reduces the searching complexity.

  • 3)

    A simple operating condition of SDVA detector: We present a simple operating condition for the SDVA detector. Under this condition, the SDVA-algorithm only searches the lattice points between the upper radius and the lower radius instead of the whole lattices points. Therefore, the ring region between the upper radius and the lower radius is defined as “radius margin”.

Our SDVA-DFE can unify the three features (SD, DF and RR). The computing complexity can be reduced by the proposed double radius constraints, upper radius (UR) and lower radius (LR). Moreover, by adjusting the values of two radiuses, the SDVA-DEF provides a trade-off between performance and complexity. In brief, the characteristics of the SDVA-DFE are adjustable performance, low computing complexity, and easy high-stage extension.

The remainder of the paper is organized as follows. In Section 2, we give some background knowledge about Sphere Decoding, MLSE-DFE and the threshold value derived in [26]. Section 3 presents the proposed SDVA-DFE algorithm. The architecture of SDVA-DFE is shown in Section 4. Section 5 shows the simulation results and Section 6 concludes this paper.

Section snippets

Review of the background

The existing works are reviewed in this section. First, we give some notations and the signal model of the normal DFE, which are defined as follows. The communication system adopted in this paper is similar to that shown in Fig. 2(a).

  • x(k) is the transmitted signal.

  • h(n) is the equivalent discrete time channel impulse response, which is linear and band-limited.

  • w(k) is Additive White Gaussian Noise (AWGN).

  • y(n) is the channel output.

  • r(n) is the output of the DFE and is expressed as:r(n)=m=0Nb1bmy(

Proposed SDVA algorithm

To derive the SDVA-algorithm, several assumptions should be made in this section.

  • The transmitted data sequence is independent and identically distributed (i.i.d.).

  • The output of the DFE can be formulated as r(n)x(n)+e(n), where e(n) is AWGN with zero mean and variance σn2. This assumption is widely accepted in many filter designs [26], [27], [28], [29], [30], [31].

  • For the sake of convenient analysis, the output detected by DFE are assumed to be correct when we need to make the decisions about

The SDVA-DFE architecture

In Section 3, an example of 2-tap SDVA-DFE with five stages is given. Nevertheless, the number of taps and stages can be extended. In this section, the general SDVA-algorithm and architecture of the SDVA-DFE are presented.

Numerical analysis and simulation results

In this section, the channel model [13] we use ish=0.5[1+cos(2π/w)21+cos(2π/w)], where w=3.3. The number of taps in FFF and FBF are 7 and 5, respectively. In general, the least mean square (LMS) algorithm is a well-known approach to obtain the filter coefficients. In our simulation, the coefficients of FFF and FBF are trained by the LMS algorithm with sufficient training sequences.

For each trial, the Gaussian random noise vector and random input bits: x{1,1} with equal probability is given.

Conclusions

In this work, we proposed a novel and effective SDVA-DFE algorithm to achieve low computing complexity. This novel DFE implementation is based on Viterbi structure with decision feedback and it is controlled by the upper radius and the lower radius. At the algorithmic level, by setting different values of the two radiuses, we can adjust the performance of SDVA-DFE between that of a normal DFE and a MLSE-DFE. At the architectural level, the SDVA-DFE can be implemented easily under the radius

Acknowledgements

This work was financially supported by the Ministry of Science and Technology of Taiwan under Grants MOST 103-2622-E-002-034, and sponsored by MediaTek Inc., Hsin-chu, Taiwan.

Hung-Yi Cheng received B.S. degree in electrical engineering and the M.S. degree in electronic engineering, in 2006 and 2008, respectively, both from Nation Tsing Hua University, Hsinchu, Taiwan. From 2009 to 2012, he was a Member of Technical Staff at Novatek corporation, Hsinchu, Taiwan, working on mixed-signal transmission IC design. He is currently working toward the Ph.D. degree in the Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan. His research

References (32)

  • J. Luo

    On low-complexity maximum-likelihood decoding of convolutional codes

    IEEE Trans. Inf. Theory

    (Dec. 2008)
  • H. Vikalo et al.

    Sphere-constrained ML detection for frequency-selective channels

    IEEE Trans. Commun.

    (July 2006)
  • B. Hassibi et al.

    On the sphere-decoding algorithm I. Expected complexity

    IEEE Trans. Signal Process.

    (Aug. 2005)
  • H. Vikalo et al.

    On the sphere-decoding algorithm II. Generalizations, second-order statistics, and applications to communications

    IEEE Trans. Signal Process.

    (Aug. 2005)
  • J.G. Proakis

    Digital Communications

    (2001)
  • Won Lee et al.

    A maximum-likelihood sequence estimator with decision-feedback equalization

    IEEE Trans. Commun.

    (Sep. 1977)
  • Cited by (1)

    • Robust adaptive algorithms for underwater acoustic channel estimation and their performance analysis

      2017, Digital Signal Processing: A Review Journal
      Citation Excerpt :

      In this paper, in order to rectify the undesirable effects of UWA channels, especially to mitigate the effects of the impulsive noise, we introduce a radical approach to adaptive channel estimation. In [19], the authors propose a low-complexity decision feedback equalizer, which employs a sphere detection-Viterbi algorithm (SDVA) with two radii in a decision feedback equalization (DFE). [19] provides a simple operating condition for the SDVA, under which the algorithm only searches a small fraction of the lattice points lying between two radii, hence, provides a lower complexity.

    Hung-Yi Cheng received B.S. degree in electrical engineering and the M.S. degree in electronic engineering, in 2006 and 2008, respectively, both from Nation Tsing Hua University, Hsinchu, Taiwan. From 2009 to 2012, he was a Member of Technical Staff at Novatek corporation, Hsinchu, Taiwan, working on mixed-signal transmission IC design. He is currently working toward the Ph.D. degree in the Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan. His research interests include digital communication and algorithms development for mixed signal.

    An-Yeu (Andy) Wu received the B.S. degree from National Taiwan University in 1987, and the M.S. and Ph.D. degrees from the University of Maryland, College Park in 1992 and 1995, respectively, all in Electrical Engineering. In August 2000, he joined the faculty of the Department of Electrical Engineering and the Graduate Institute of Electronics Engineering, National Taiwan University (NTU). His research interests include low-power/high-performance VLSI architectures for DSP and communication applications, adaptive/multirate signal processing, and System-on-Chip (SoC)/Network-on-Chip (NoC) platform. He has published more than 190 refereed journal and conference papers in above research areas, together with five book chapters and 16 granted US patents.

    From August 2007 to Dec. 2009, he was on leave from NTU and served as the Deputy General Director of SoC Technology Center (STC), Industrial Technology Research Institute (ITRI), Hsinchu, TAIWAN, supervising Parallel Core Architecture (PAC) VLIW DSP Processor and Multicore/Android SoC platform projects. In 2010, Dr. Wu received “Outstanding EE Professor Award” from The Chinese Institute of Electrical Engineering (CIEE), Taiwan. Prof. Wu is elevated to IEEE Fellow in 2015 for his contributions to “DSP algorithms and VLSI designs for communication IC/SoC.”

    This work was financially supported by the Ministry of Science and Technology of Taiwan under Grants MOST 103-2622-E-002-034, and sponsored by MediaTek Inc., Hsin-chu, Taiwan.

    View full text