A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX

https://doi.org/10.1016/j.eswa.2013.07.087Get rights and content

Highlights

  • Proposed and implemented a low power and low phase noise CMOS integer-N frequency synthesizer.

  • A low phase noise of −121.1 dBc/Hz VCO is proposed and results in a better FOM.

  • P counter only pulse swallow counter is proposed to low power consumption.

  • High speed and low power TSPC counter is proposed.

  • A successful chip fabrication and measurement of the proposed design.

Abstract

This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22 GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is −121.6 dBc/Hz at 1 MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1 mW. The chip with an area of 1.048 × 1.076 mm2 is fabricated in a TSMC 0.18 μm CMOS 1P6M technology process.

Introduction

With the unprecedented demand in wireless broadband service, WiMAX (World Interoperability for Microwave Access) is one of the promising communication techniques to deliver the last mile wireless broadband access as an alternative to cable and ADSL. The characteristics of wireless broadband services include large data capacity and capability of long distance transmission. Based on the IEEE 802.16 standard WiMAX becomes the developing target in the mobile communication industry all over the world, and WiFi (Wireless fidelity) is one of the popular wireless communication techniques. With the advantage of WiFi technology, which is easy to deploy at low cost, users are able to access the service for up to 300 ft from the access point. However, the weakness of WiFi limits the development such as the mobility and interference from other systems. Therefore, WiMAX can be a replacement of WiFi and becomes the advanced wireless communication technique (http://www.wimaxforum.org/home).

WiMAX is expected to provide both fixed and portable wireless broadband connectivity without the need of a base station. In a typical cell radius deployment of 3–10 km, WiMAX can provide a capacity of up to 40 Mbps per channel for fixed and portable access applications. Three spectrum bands are adopted for the global WiMAX deployment: the first one is the unlicensed 5 GHz band (5.725–5.850 GHz), the second one is the licensed 3.5 GHz band for fixed mobile, and the third one is the licensed 2.5 GHz band for mobile users. In this paper, the proposed design is intended for wireless communication system in an unlicensed 5 GHz band. For wireless communication systems, transceivers are the primary components to transmit or receive, data and the stringent performance requirements become major challenges for circuit designers. In the front-end circuit of transceiver, frequency synthesizer is one of the most critical circuit blocks in wireless communication device. The fundamental function of the frequency synthesizer is to generate the carrier frequency for both the transmitter and the receiver. Therefore, an excellent design of the frequency synthesizer not only enhances the performance but also reduces the power consumption in the entire circuit (http://www.wimaxforum.org/home).

A frequency synthesizer based on the PLL structure is presented. A novel VCO is proposed to meet the stringent requirement of WiMAX. The architecture of the conventional PLL frequency synthesizer can be classified into two categories: one is the ring-based VCO PLL and the other is the LC-based VCO PLL. In the RF application, LC-based VCO PLL is preferred because it exhibits a better phase noise performance compared to that of ring-based VCO PLL (Hajimiri & Lee, 1999). To achieve a high performance LC-based PLL requires discreet design of the conflicting requirements among low phase noise, low power consumption, and fast locking time. The proposed VCO is designed to optimize the trade-off problems between phase noise and power consumption. The proposed VCO is integrated into a 5-GHz PLL frequency synthesizer for WiMAX/WLAN application. The conventional frequency synthesizer is shown in Fig. 1. This frequency synthesizer employs the integer-N architecture, and consists of a PFD, a charge pump, a low pass filter, a frequency divider, and a VCO. The frequency divider provides the divide ratio M of 513–522. The output frequency of VCO is divided down to 5 MHz by the frequency divider. Then the Fdiv is compared with the reference frequency Fref by PFD. The output voltage of the charge pump (CP) can be charged or discharged by up and down signals generated by PFD. Therefore, the tuning voltage and hence the frequency of the VCO can be adjusted by PFD and CP based on the PLL’s loop condition. In this application, the RF frequency of the antenna with the front-end circuit range from 5.725 to 5.825 GHz (IEEE Standard for Local and Metropolitan Area Networks – Part 16). Ten channels are designed with a bandwidth of 10 MHz in each channel and the supply voltage is 1.5 V.

In Section 2, detailed design of the proposed VCO is described. The circuit implementations of each building block in the proposed LC-VCO PLL frequency synthesizer are presented in Section 3. The simulated and measured results and performance comparison among different designs are shown in Section 4. Finally, conclusion is given in Section 5.

Section snippets

Voltage Controlled Oscillator

The VCO is a critical component in the communication systems as low phase noise, low power consumption, and low cost are the major design challenges for the RF front-end circuit in wireless transceiver applications. Generally, a high performance VCO is integrated within a PLL system to compose a frequency synthesizer. Frequency synthesizer combines with the local oscillator that mixes with the incoming RF signal to create a lower frequency signal. The signal generated by the VCO must be

Frequency synthesizer

The channel spacing of the frequency synthesizer used in WiMAX transceiver is 10 MHz. Therefore, an integer-N architecture is adopted in the proposed frequency synthesizer. The architecture of the proposed frequency synthesizer is a type-II second-order loop as shown in Fig. 1. For a system with 10 MHz channel spacing and ten channels, the reference frequency in the proposed frequency synthesizer is set to 5 MHz. The division ratio of frequency divider M counting from the output of the high speed

Simulation results and measurements

We used “SPICE” to simulate the proposed circuit. The SPICE model used in the simulation is TSMC 0.18 μm Mixed-Signal technology provided by Chip Implementation Center (CIC). The circuit is biased at a 1.5 V supply voltage.

The measured tuning range of the proposed VCO is shown in Fig. 21. By observing Fig. 21, the tuning range of the proposed VCO can be ranged from 5.12 to 5.26 GHz with respect to 1.5 to 0 V tuning voltage. The phase noise simulation is shown in Fig. 22. The simulated phase noise

Conclusion

An integrated 5 GHz frequency synthesizer with the LC VCO is designed. The design has been fabricated by a TSMC 0.18-μm 1P6 M CMOS technology. The proposed LC VCO employs the noise filter and the memory reduction tail transistor to reduce phase noise and power consumption. The proposed PLL can be used for WiMAX 5 GHz unlicensed band which includes 10 communication channels with a 10 MHz bandwidth in each channel. The frequency divider combines the S and P counters into a single P counter with the

Acknowledgments

Authors would like to acknowledge financial support of the National Science Council (Taiwan, Republic of China), under the Grant numbers NSC100-2221-E-110-059 and NSC101-2221-E-110-098. Furthermore, authors would like to express greatest gratitude to CIC (Chip Implementation Center) of NAPL (National Applied Research Laboratories), Taiwan, for their valuable chip fabrication service.

References (43)

  • M. Alioto et al.

    Design of high-speed power-efficient MOS current-mode logic frequency dividers

    IEEE Tranactions on Circuits and Systems – II: Express Briefs

    (2006)
  • P. Andreani et al.

    On the use of MOS varactors in RF VCO’s

    IEEE Journal of Solid-State Circuits

    (2000)
  • C.C. Boon et al.

    RF CMOS low-phase-noise LC oscillator through memory reduction tail transistor

    IEEE Journal of Solid-State Circuits

    (2004)
  • A. Bounomo et al.

    The effect of parameter mismatches on the output waveform

    International Journal of Circuit Theory and Applications s

    (2010)
  • S.P. Bruss et al.

    A 5-GHz CMOS type-II with low KVCO and extended fine-tuning range

    IEEE Transactions on Microwave Theory and Techniques

    (2009)
  • J. Craninckc et al.

    A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors

    IEEE Journal of Solid-State Circuits

    (1997)
  • P.Y. Deng et al.

    A 5-GHz CMOS synthesizer with an injection-locked freqeuncy divider and differential switched capacitors

    IEEE Tranactions on Circuits and Systems – I: Regular Papers

    (2009)
  • S.L.J. Gierkink et al.

    Intrinsic 1/f device noise reduction and its effect on phase noise in CMOS ring oscillators

    IEEE Journal of Solid-State Circuits

    (1999)
  • Gil, J., & Shin, H. (2002). A 2.4GHz fully integrated CMOS quadrature VCO. In IEEE Asia-Pasific SoC conference (Vol. 5,...
  • A. Hajimiri et al.

    The design of low-noise oscillators

    (1999)
  • D. Ham et al.

    Conecpts and methods in optimization of integrated LC VCOs

    IEEE Journal of Solid-State Circuits

    (2001)
  • E. Hegazi et al.

    A filtering technique to lower LC oscillator phase noise

    IEEE Journal of Solid-State Circuits

    (2001)
  • C.M. Hsu et al.

    A low-noise wide-BW 3.6-GHz digital ΔΣ fractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation

    IEEE Journal of Solid-State Circuits

    (2008)
  • ...
  • Q. Huang et al.

    Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks

    IEEE Journal of Solid-State Circuits

    (1996)
  • T.H. Huang et al.

    A 1 V 2.2 mW 7 GHz CMOS quadrature VCO using current and cross-coupled transformer-feedback technology

    IEEE Microwave and Wireless Componentes Letters

    (2008)
  • IEEE standard for local and metropolitan area networks – part 16: Air interface for fixed broadband wireless access...
  • S.L. Jang et al.

    An integrated 5–2.5-GHz direct-injection locked quadrature LC VCO

    IEEE Microwave and Wireless Components Letters

    (2007)
  • S.L. Jang et al.

    A 5.6 GHz low power balanced VCO in 0.18 μm CMOS

    IEEE Microwave and Wireless Componentes Letters

    (2009)
  • A. Jannesari et al.

    Sinusoidal shaping of the ISF LC oscillators

    International Journal of Circuit Theory and Applications

    (2008)
  • E.A.M. Klumperink et al.

    Reducing MOSFET 1/f noise and power consumption by switch biasing

    IEEE Journal of Solid-State Circuits

    (2000)
  • Cited by (0)

    View full text