Direct approaches to exploit many-core architecture in bioinformatics

Abstract

Current trends in computer programming look for solutions in the challenging task of porting and optimizing existing algorithms to many-core architectures with tens of Central Processing Units (CPUs). Yet, the lack of standardized general-purpose parallel programming and porting methodologies represents the main bottleneck on these developments. We have focused on bioinformatics applied to genomics in general and the so-called “Next-Generation” Sequencing (NGS) in particular, in order to study the viability and cost of porting and optimizing well known algorithms to a many-core architecture. Three different methods are tackled in order to implement existing algorithms in Tile64, corresponding to a microprocessor containing 64 CPUs, each of them being capable of executing an independent Linux operating system. Three different approaches have been explored: (i) implementation of the Needleman–Wunsch/Smith–Waterman pairwise aligner from scratch; (ii) direct translation of the Message Passing Interface (MPI) C++ ABySS assembly algorithm with changes on the communication layer; and (iii) migration of the ClustalW tool, parallelizing only the most time-consuming stage. The performance-gain/development-cost tradeoffs indicate that the Tile64 microprocessor has the potential to increase the performance of bioinformatics in an unprecedented way for a standalone Personal Computer (PC). Yet, the effective exploitation of these parallel implementations requires a detailed understanding of the peculiar many-core characteristics when migrating previous non-parallel source codes.

Introduction

Nowadays, high-performance processing cannot be understood without new Chip Multiprocessors (CMPs), which are being actively developed. Amongst such chips are the Graphics Processing Units (GPUs) with hundreds of cores [1] and the Sony–IBM–Toshiba Cell Broadband Engine Architecture (CBEA) [2], which allow us to render complex animations and provide as well enough computing power to perform other calculus-intensive tasks [3]. This line is exploited by supercomputing blade systems like the IBM BladeCenter server platform [4] and the Nvidia Tesla [5]. Yet, such products require detailed programming methodologies and architecture optimizations, which are much more complex than the ones of the single Central Processing Units (CPUs) [6], [7]. A comparison between these different programming approaches and an attempt to automate such processes can be found at [8]. Other companies are working in CMP and multithreaded many-core microprocessors, like the Intel Tera-scale Processor with 80 cores [9], Single-chip Cloud Computing (SCC) [10] with 48 cores, the “Knights Ferry” [11] with 32 cores, the Xeon E7 with 10 cores and two threads per core [12], the Sun Microsystems UltraSPARC T2 Pro with eight cores and eight threads per core [13], the Adapteva Epiphany IV (64 cores) [14] and the Tilera Tile64 microprocessor, as explained below.

The TilExpress-20G cards include a many-core Tile64 microprocessor with 64 tiles (cores) at 866 MHz, 8 GB of RAM and two 10 GB Ethernet ports. Though they were initially designed for networking applications, video encoding [15] and streaming broadcasts (thanks to their high communication bandwidth and scalability), we have already demonstrated the usefulness of such architecture for bioinformatics [16], [17]. We are applying such developments for quality control, traceability and fraud prevention of olive oil [18], as well a other genomics approaches of our research group on Agri-Food Biotechnology.

Other works have focused on fine-tuning intensive processing bioinformatics algorithms to platforms like GPU [19], [20], [21] or the above mentioned CBEA [22], obtaining better performances than with single CPU implementations, as a result of their parallelization factor. The main difference between these developments and the present work is that Tile64 actually contains many CPUs (in the sense that each one of them is able to execute a standalone operating system). In contrast, the so-called many-core GPU contains very restricted processing units, unable to execute a whole complex algorithm on their own. Thus, many of the bioinformatics algorithms ported to the GPU architectures show extraordinary speed-ups but, due to the restricted resources, usually only work well with some specific data, sharply decreasing their performance when applied to a wider range of input data. For instance, in the case of sequence alignments, only short sequences (typically, peptides) are allowed, precluding their application for larger projects involving nucleic acid data (e.g., genomics). On the other hand, the CBEA integrates two kinds of microprocessors: one Power Processing Element (PPE) and eight Synergistic Processing Elements (SPE); whereas Tile64 contains a homogenous matrix of 8×8 tiles. This architecture offers the opportunity to evaluate such a system to evaluate the effort that must be dedicated to obtain a working parallelized algorithm on it, and the achieved performance according to the development and code migration approach used, as explained below. Indeed, this work focuses more on evaluating the possible migration approaches, and less on getting the maximum possible performance (which in any case may require a more time-consuming approach).

In order to further evaluate the suitability of the Tile64 architecture in the field of bioinformatics, we have tested three commonly used algorithms by life-science researchers: (i) pairwise sequence alignments: (ii) multiple sequence alignments; and (iii) de novo genome assembly. Taking into account the Tile64 software development characteristics [16], three different approaches regarding porting efforts have been considered; namely: (i) an implementation from scratch of a dynamic programming algorithm like the Fast Linear-Space Alignment (FastLSA) [23], with a parallel strategy for pairwise alignments; (ii) a half-way solution, where a customized communication layer replaces the Message Passing Interface (MPI) in the Assembly By Short Sequences (ABySS) algorithm [24]; and (iii) a slightly modified implementation of a parallel multiple sequence aligner (ClustalW) [25]. Each proposal is discussed in terms of the trade-offs between the development efforts and the achieved performance. Such strategy allows noting several mandatory principles for efficient many-core developments.

On the other hand, the term many-core is used as a synonym of many-core CPU and this should not be confused with many-core and General-Purpose GPU (GPGPU). To avoid confusions, the manufacturers of many-core CPUs have coined a new term: tile. This term relates to the geometry that can be visually observed in the die of the chip; it is a reminiscence of how a tile contributes to complete a mosaic. The shape of the die provides a preliminary idea of how different are the many-core CPUs vs the GPUs. Table 1 shows the main differences between these technologies from a programming and performance point of view. The last row of the table visually notes these differences by comparing die-shots from these platforms. This may help to understand that the parallelization strategies are indeed drastically different. Thus, GPGPU cores are specialized in executing small threads rather than huge tasks (such as a whole operating system) and this simplicity allows an easier integration of hundreds of these computing elements in a single die; whereas the many-core CPUs have just tens of tiles nowadays. So then, the strategy when porting algorithms to GPUs is to generate as much execution threads as possible, in order to maximize the number of cores working at a given time.

These large differences among many-core CPUs and GPUs make very difficult any comparison between the performance and capabilities between such architectures. Actually, they should be considered as complementary rather than competitors, as is noted in Table 1. Tilera’s approach is not the only one following this new tile-based computing paradigm. Intel has joined the bandwagon of this technology with Single-chip Cloud Computing (SCC) [10], a platform with hardware-based message-passing capabilities and a whole operating system running in each tile. Nevertheless, Intel’s platform is nowadays in an academic and research stage, Tilera’s platform being the only one commercially available. Another example is the Adapteva Epiphany IV chip, which should be available by later 2012.