Energy-aware task migration for multiprocessor real-time systems

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Abstract

A task migration method is proposed for energy savings in multiprocessor real-time systems. The method is based on the portioned scheduling technique which classifies each task as a fixed task or a migratable task. The basic task migration problem with specific parameters is formulated as a linear programming problem to minimize average power. Then, the method is extended to more general case with a complete migration algorithm. Moreover, a scheduling algorithm is proposed for migratable tasks. Simulation results on two processor models demonstrated significant energy savings over existing methods.

Introduction

Power consumption has become one of the major concerns in today’s embedded system design. Reducing power or energy consumption can extend battery lifetime of portable systems, decrease chip cooling costs, and increase system reliability. As one of the most effective methods for energy savings, the dynamic voltage scaling (DVS) has been extensively studied on uniprocessor so far. However, the power problem still exists, which limits the further improvement of performance on the uniprocessor. As a promising approach to achieve higher performance and lower power consumption, multiprocessors have attracted much attention recently. Meanwhile, the energy-aware real-time task scheduling on multiprocessors is becoming an important issue. There are mainly two approaches to schedule real-time tasks on the multiprocessor: global scheduling and partitioned scheduling. The global scheme uses a global scheduler for all processors to assign tasks to the processor online, whereas the partitioned scheme uses a dedicated scheduler for each processor, and tasks are assigned to particular processors offline. Generally, the global scheme permits task migration between processors when dispatching a task. Conversely, normal partitioned scheme does not support task migration. Once a task is assigned to a processor, it cannot run on any other processors. In current real-time multiprocessor systems, the partitioned scheme is common because of its simplicity and ease of implementation  [1], [2]. In other words, it reduces a multiprocessor scheduling problem to a set of uniprocessor ones. For this reason, this work is targeted at the partitioned scheduling technique.

Several studies have been made on the energy-aware partitioned scheduling in the DVS-equipped multiprocessor systems. It was proven that the total energy consumption of the multiprocessor is minimized under the earliest-deadline-first (EDF) scheduling in the case that the workload is perfectly balanced among the processor cores  [3], [4]. Because the problem of energy-aware task scheduling is NP-hard  [1], several heuristics were employed in the literature. It was known that the worst-fit decreasing (WFD) heuristics can achieve more energy savings than other heuristics because it leads to more balanced workload than other heuristics  [1]. In fact, it has been proven that the WFD algorithm can achieve 1.5-approximation than the optimal algorithm for load balancing problem  [5]. Approximate algorithm based on WFD with 2-approximation for the energy-efficient scheduling problem was also introduced in  [6] by considering leakage energy. However, the above methods assume an ideal processor with continuously selectable speeds and zero idle power. As a result, for real processors with discrete speeds and nonzero idle power, these methods cannot achieve the maximal energy savings  [7]. A significant advantage of the above algorithms is that the DVS overhead is avoided completely because they assign one speed for all tasks allocated on the same core. In contrast, algorithms for assigning different speeds to the tasks on the same core have also been proposed in  [8], [9], [10]. However, the DVS overhead cannot be ignored in these algorithms due to frequently runtime voltage/frequency (V/F) transition. As summarized in the  [11], commercial DVS uniprocessor chips typically require hundreds of microseconds for each V/F transition.

Recently, task migration between processors was recognized as an effective method for improving the worst-case system utilization bound on the partitioned scheduling  [12], [2]. For example, the Earliest Deadline Deferrable Portion (EDDP) method can improve the worst-case bound from 50% to 65% via task migration  [2]. In addition, task migration was also proposed for thermal management  [13]. Moreover, a workload aware task migration algorithm was proposed to reduce energy consumption, which is based on a global scheduling algorithm, and migrates a task from high speed processor to low speed one based on actual task execution time  [14]. As mentioned earlier, this paper focus on the partitioned scheduling algorithm and assumes known worst case execution time for scheduling, which is significantly different with existing migration algorithm. In this paper we show that even for partitioned scheduling, there are opportunities for energy savings via task migration. As an example, Fig. 1 shows the potential for energy savings in the partitioned scheduling via task migration in which the width of rectangle indicates the magnitude of task utilization. In this example, although the utilizations of two tasks are only 0.45 and 0.16, higher speeds of 0.6 and 0.4 have to be used due to deadline constraints and discrete speeds. As can be seen, some energy has been wasted because even if the processor Py has left capacity of 0.24 for running task at the low speed of 0.4, the large task has to be run at high speed of 0.6 on the processor Px if task cannot be migrated. For this reason, if we can split the large task i into two portions, and migrate partial utilization of task i from the high speed processor to the low speed one, total energy can be saved. According to our approach, energy can be reduced by 16% when migrating 0.24 utilization of task i from processor Px to processor Py.

In this work, we propose algorithms to solve the above task migration problem for maximal energy savings on multiprocessor real-time systems. The approach includes two phases. In the design time phase, tasks are allocated to processors first without migration, then migration parameters are calculated and stored by using the proposed migration algorithm if energy can be saved via migration. In the runtime phase, a modified EDF based scheduler is employed to schedule the processor with migratable task according to the stored migration parameters. The main contributions of this paper are as follows. (1) A portioned based task migration model is proposed. The model has limited migration cost because task migration is applied only in case that energy can be saved, and the maximal number of migratable tasks is limited to m/2 where m is the number of processor cores. (2) For a selected task for migration, the energy-aware task migration problem is formulated as a linear programming problem and a novel optimal solution is proposed. Moreover, the above results are extended to more general case with a complete migration algorithm. (3) Energy savings are evaluated using simulation on a synthetic multiprocessor. The results showed that the proposed migration method can achieve better energy reduction than existing methods.

The rest of the paper is organized as follows. Section  2 introduces the system models. Section  3 presents the proposed migration algorithms. Section  4 gives experimental results. Finally, Section  5 concludes the paper.

Section snippets

Processor power model

Although many existing publications on energy-aware multiprocessor scheduling assumed a multiprocessor with dynamic core-level V/F scaling (DCVFS) capability, few commercial or even test embedded multiprocessors chip with this capability can be found in practice. This status was also declared in the  [16]. The possible reasons include the increased design complexity, test cost, and reliability problem especially for the embedded systems. Recently, it has been reported that the ARM11 MPcore

Proposed migration model and algorithms

As mentioned before, the proposed approach for energy-aware task migration includes two phases. In design time phase, for a given task set and target multiprocessor, a heuristic algorithm is utilized first to allocate tasks to processors without migration. The algorithm can save both dynamic and static power by considering discrete speeds and nonzero idle power. Then, complete migration algorithm is applied based on the allocation results. The migration is conducted only when the energy can be

Experimental results

To evaluate the efficiency of proposed algorithms, experiments are conducted on a synthetic multiprocessor with homogeneous architecture. This multiprocessor consists of some identical processor cores with the power models as shown in Table 1. Task sets with different utilizations are randomly generated and are assumed to run on this multiprocessor.

The energy consumption of different algorithms is measured as a function of two task set parameters: the average utilization Uave and the maximal

Conclusion

In this work, we proposed energy-aware task migration for real-time multiprocessor systems. The method has several advantages over existing methods. First, the proposed migration model is simple for implementation. Second, the migration cost in terms of number of migratable tasks is limited because the migration is performed only in case that energy can be saved. Finally, the task is split in such a way that the total energy after task migration is minimized. Simulations on two commercial

Acknowledgment

This work was supported by JSPS KAKENHI Grant No. 24500036.

Gang Zeng is an Associate Professor at the Graduate School of Engineering, Nagoya University. He received his Ph.D. degree in Information Science from Chiba University in 2006. From 2006 to 2010, he was a Researcher, and then Assistant Professor at the Center for Embedded Computing Systems (NCES), the Graduate School of Information Science, Nagoya University. His research interests mainly include power-aware computing and real-time embedded system design. He is a member of IEEE and IPSJ.

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    Gang Zeng is an Associate Professor at the Graduate School of Engineering, Nagoya University. He received his Ph.D. degree in Information Science from Chiba University in 2006. From 2006 to 2010, he was a Researcher, and then Assistant Professor at the Center for Embedded Computing Systems (NCES), the Graduate School of Information Science, Nagoya University. His research interests mainly include power-aware computing and real-time embedded system design. He is a member of IEEE and IPSJ.

    Yutaka Matsubara is an Assistant Professor at the Center for Embedded Computing Systems (NCES), the Graduate School of Information Science, Nagoya University. He received his Ph.D. degree in Information Science from Nagoya University in 2011. He was a Researcher from 2009 to 2011 at Nagoya university, and was a designated Assistant Professor in 2012. His research interests include real-time operating systems, real-time scheduling theory, and embedded system design for safety and security. He is a member of IEEE and IPSJ.

    Hiroyuki Tomiyama received his Ph.D. degree in computer science from Kyushu University in 1999. From 1999 to 2001, he was a Visiting Postdoctoral Researcher with the Center of Embedded Computer Systems, University of California, Irvine. From 2001 to 2003, he was a Researcher at the Institute of Systems and Information Technologies/KYUSHU. In 2003, he joined the Graduate School of Information Science, Nagoya University, as an Assistant Professor, and became an Associate Professor in 2004. In 2010, he joined the College of Science and Engineering, Ritsumeikan University as a Full Professor. His research interests include design automation, architectures and compilers for embedded systems and systems-on-chip. He currently serves as Editor-in-Chief for IPSJ Transactions on SLDM. He has also served on the organizing and program committees of several premier conferences including ICCAD, DAC, DATE, ASP-DAC, CODES + ISSS, and so on. He is a member of ACM, IEEE and IPSJ.

    Hiroaki Takada is a Professor at the Department of Information Engineering, the Graduate School of Information Science, Nagoya University. He is also the Executive Director of the Center for Embedded Computing Systems (NCES). He received his Ph.D. degree in Information Science from the University of Tokyo in 1996. He was a Research Associate at the University of Tokyo from 1989 to 1997, and was an Lecturer and then an Associate Professor at Toyohashi University of Technology from 1997 to 2003. His research interests include real-time operating systems, real-time scheduling theory, and embedded system design. He is a member of ACM, IEEE, IPSJ, JSSST, and JSAE.

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