Novel bit-parallel multiplier for GF(2m) defined by all-one polynomial using generalized Karatsuba algorithm

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Highlights

  • We construct a bit-parallel multiplier for AOP based on a generalized Karatsuba algorithm.

  • We examine the influence about multiplier efficiency with respect to decomposition of polynomial degree.

  • The lower bound of the space complexity is m2/2+O(m{3/2})+O(m).

  • The time complexity nearly matches the fastest multiplier for AOP.

Abstract

In this paper, a novel bit-parallel multiplier for finite field GF(2m) defined by irreducible all-one polynomial (AOP) is proposed. We utilize a generalized Karatsuba algorithm (KA) to reduce the number of coefficient multiplications and the redundant representation to simplify polynomial modular reduction. Explicit formulae with respect to the space and time complexity of the proposed multiplier are given. By evaluating the asymptotic lower bound of the complexity, the selection of the generalized KA and decomposition of m are investigated to obtain the optimal result. Consequently, theoretical complexity analysis proved that our architecture requires even fewer logic gates than previous proposals, while it still maintains relatively low time delay. For a special class of GF(2m) generated with AOPs, it even matches the best known multipliers found in the literatures.

Introduction

Efficient bit-parallel multipliers over GF(2m) are frequently desired by some public-key cryptosystems [1], [2]. Generally, the multiplier efficiency is evaluated by the space and time complexity, where the former is usually defined as the number of AND/XOR gates and the latter is defined as the operation time of the multiplier circuit. The irreducible polynomials used to define GF(2m) always have great influence on the performance of related multipliers. The irreducible polynomials such as all-one polynomial (AOP) [3], [4], trinomial [5] and pentanomial [6] are fully studied for efficient implementation.

Since AOP can obtain a trade-off between time and space complexity, a number of bit-parallel multipliers using irreducible AOPs are proposed during recent years. These proposals are based on polynomial basis (PB) [3], normal basis (NB) [4], [8], [9], weakly dual basis [10] and some other non-conventional basis. The most efficient multipliers among above proposals cost m2 AND gates, m21 XOR gates with TA+(1+log2(m1))TX time delays. Some other special multipliers based on AOPs have also been proposed in [7], [12], [13], [14], [15].

In [16], a low-complexity bit-parallel multiplier for AOP was proposed by Chang et al. where redundant representation is applied instead of PB to represent finite field elements. The redundant representation [17] was derived from the minimal cyclotomic ring where GF(2m) is represented as a subring of a residue class ring F2[x]/(xn+1) with n>m. It provides free squaring operation and elimination of the modular reduction step with a small increase of circuit gates. If GF(2m) is defined by an irreducible AOP, the ring has a minimal redundant bits as xm+1=1. Chang used this representation combined with Karatsuba algorithm (KA) to construct high efficient polynomial multiplication. As a result, their approach only requires approximately 3/4 circuit gates compared with previous ones, while the corresponding time complexity is nearly the same.

Based on a three-term KA [19], [20], we have improved the above approach and constructed a bit-parallel multiplier for AOPs with lower complexity [18]. In this contribution, we focus on the generalization of our previous scheme. By introducing a n-term KA mentioned in [19] and utilizing a decomposition of the AOP degree m, a novel bit-parallel AOP multiplier is developed. Explicit formulae and complexity analysis are given. We then show in detail how to select the most suitable KA and decomposition of m to obtain the optimal results. Consequently, it is argued that for a number of irreducible AOPs, our multipliers have almost the same time complexity, but lower space complexity compared with the best known proposals in the literatures.

The rest of the paper is organized as follows: In Section 2, we briefly review the redundant representation for GF(2m) generated with the AOPs and introduce the n-term KA mentioned in [19]. Then we describe a new bit-parallel multiplier architecture by combing with redundant representation and the n-term KA in Section 3. In Section 4, we further analyze its complexity and present a comparison between the proposed multiplier and some others. Finally, some conclusions are drawn.

Section snippets

Preliminary

In this section, we briefly review the notion of redundant representation and the generalized Karatsuba algorithm (KA). The redundant representation was firstly introduced by Itoh and Tsujii [17] and then used in the design of many multipliers [21], [22], [23]. The basic idea was to embed the finite field into the minimal cyclotomic ring F2[x]/(xn+1) and perform all the field arithmetic operations in such a ring. Thus the field elements using ring representation have certain redundant bits.

Multiplier architecture based on n-term Karatsuba algorithm

Let f(x) be an irreducible AOP over F2 and x be a root of f(x). In the field GF(2m) generated with f(x), we represent the field element UGF(2m) using redundant representation asU=i=0muixi, where uiGF(2). Note that the irreducible AOP over F2 exists if and only if m+1 is prime and 2 is primitive modulo m+1 [1]. Thus it cannot apply the n-term KA to the m+1-bit polynomial multiplication directly. Here, we divide such polynomial into two parts and deal with them separately. Suppose that A,B are

Theoretic complexity

Since the parameters n,k,r can be chosen freely, we select r as a small integer which can be omitted and replace k by (m+1r)/n in the complexity formulae presented in Section 3. Then the area complexity is expressed, for simplicity, as:# AND: (12+12n)m2+O(m),# XOR: (12+12n)m2+2nm+O(m). Since the gate AND and XOR are both basic logic gates in digital electronics, we take into account the number of circuit gates without distinguish AND and XOR. It is easy to see that if m2n=2nm, namely, n=(m2)1/2

Conclusion

In this paper, a high efficient bit-parallel multiplier for GF(2m) defined by the irreducible AOP has been proposed. We use the redundant representation to simplify the modular reduction. Meanwhile, m is decomposed into nk+r1 and a n-term KA is applied to reduce the complexity of polynomial multiplication. It has shown that our multiplier compares favorably to the previous proposed multipliers in terms of space complexity. For a class of fields where there exits an optimal decomposition, the

Acknowledgements

The authors would like to thank anonymous referees and the editor for their great help in improving the paper.

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