Modelling and performance study of finite-buffered blocking multistage interconnection networks supporting natively 2-class priority routing traffic
Introduction
Multistage interconnection networks (MINs) with crossbar switching elements (SEs) are often used in the context of multiprocessor computer architecture for the interconnection of processors and memory modules (Chang-hoon and Sung-chun, 1997), (Josep and Zheng, 1997). MINs are also increasingly adopted for implementing the switching fabric of high-capacity communication processors, including ATM switches, gigabit Ethernet switches and terabit routers (Atiquzzaman and Chen, 1999, Elizabeth and Hing, 2004, Saleh and Atiquzzaman, 2000, Saleh and Atiquzzaman, 2001, Zhou and Atiquzzaman., 2002). MINs owe their popularity both to operational features they deliver, such as the ability to route multiple communication tasks concurrently, and to the low cost/performance ratio they achieve. The family of multistage interconnection networks includes several major categories, such as Omega, Generalized Cube, Benes, Batcher Banyan etc; of these, MINs with the Banyan (Goke and Lipovski, 1973) property are more widely adopted, since non-Banyan MINs are, in general, more expensive than Banyan ones and more complex to control.
The performance of the communication infrastructure that interconnects the system's elements (nodes, processors, memory modules etc.) has been recognized as a critical factor for overall system performance, both in the context of parallel and in the context of distributed systems. As a result, much research has been conducted, targeting to identify the factors that affect the communication infrastructure's performance and provide models for performance prediction and evaluation. Two major directions have been taken to this end: the first employs analytical models based either on Markov models or on Petri-nets, while the second uses simulation techniques. These works enable network designers to estimate network performance before it is actually implemented, allowing thus network design tuning and adjustment of parameters. Using the insights from this procedure, network designers may craft efficient systems, tailored to the specific requirements of the system under implementation with a minimal cost, since the actual implementation decisions are deferred until all operational parameters have been determined.
In this paper we propose a novel approach to model the operational behaviour of a 2-priority class MIN, which takes into account the previous and the current state of both queues (high and low priority) of each switching element, leading thus to more accurate results. The modelling scheme is complemented with equations expressing the probability for each state transition, giving a complete analytic framework for 2-class priority MIN performance behaviour. Simulation experiments are also conducted to estimate the MIN performance under various traffic loads, buffer lengths, high/low priority traffic ratios and MIN sizes (number of stages). The findings of this paper can be used by network designers to gain insight on the impact of each MIN design parameter on the overall MIN performance and to select the optimal MIN configuration for the needs of their environment.
The remainder of this paper is organized as follows: Section 2 overviews related work in the area of network performance evaluation and priority schemes, while in Section 3 we present the proposed 2-class priority scheme, we describe its operation and give its analytical system of equations. Thus, a novel 5-state and 6-state buffer model for high and low priority queues, respectively is employed. Subsequently, in Section 4 we present the performance criteria and parameters related to the network. Section 5 presents and discusses the results of our performance analysis, which has been conducted through simulation experiments, while Section 6 provides the concluding remarks and outlines future work.
Section snippets
Related work
Single priority queuing systems in the context of MIN performance evaluation have been extensively studied and are reported in numerous publications. For example, (Garofalakis and Stergiou, 2008, Jenq, 1983, Mun and Youn, 1994, Theimer et al., 1991, Vasiliadis et al., 2009) study the throughput and system delay of a MIN assuming the SEs have a single input buffer, whereas the performance of a finite-buffered MINs is studied, among others, in Garofalakis and Stergiou (2010), Lin and Kleinrock
Modelling and analytical equations for a 2-class packet priority MIN
A Multistage interconnection network (MIN) can be defined as a network used to interconnect a group of N inputs to a group of M outputs using several stages of small size switching elements (SEs) followed (or preceded) by link states. Its main characteristics are its topology, routing algorithm, switching strategy and flow control mechanism. A MIN with the Banyan property is defined in Goke and Lipovski (1973) and is characterized by the fact that there is exactly a unique path from each source
Performance evaluation methodology
In order to evaluate the performance of a (N×N) MIN with n=logcN intermediate stages of (c×c) SEs, we have employed discrete time simulation. In the following text, T denotes a relatively large time period divided into u discrete time intervals (τ1, τ2,…,τu). Performance metrics under the discrete time model may be defined as follows:
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Average throughput Thavg is the average number of packets accepted by all destinations per network cycle. This metric is also referred to as bandwidth. Formally, Th
Simulation results and discussion
The performance of MINs is usually determined by modelling, using simulation (Tutsch and Brenner, 2003) or mathematical methods (Tutsch and Hommel, 2002). In this paper we evaluated the network performance using simulation experiments due to the complexity of the model. For this purpose we developed a special simulator in C++, capable of handling 2-class priority MINs. The simulator has several parameters such as the buffer-length, the number of input and output ports, the number of stages, the
Conclusions
In this paper we have addressed the performance evaluation of 2-class priority MINs. We have modelled an analytical system of equations, employing a scheme that takes into account both the previous and the last state of the switching elements, providing thus better accuracy than schemes considering only the last state. We have also evaluated the performance of 2-class priority MINs under varying offered loads and buffer sizes, considering the high-priority and low-priority packet classes, as
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