Towards single layer quantum-dot cellular automata adders based on explicit interaction of cells
Introduction
CMOS technology has encountered serious challenges in terms of power consumption, physical dimensions, and leakage current [1]. These deficiencies have led to significant efforts to find appropriate alternatives and among the proposed solutions, nanoscale technologies such as tunneling phase logic (TPL), single electron tunneling (SET) and Quantum Cellular Automata (QCA) have received considerable attention [2], [3].
QCA would be of significant interest to researchers due to its attractive characteristics such as low power consumption, high speed operation and small dimensions. QCA circuits are made up of QCA cells which contain electrons and binary information is encoded by these electrons rather than current (CMOS is current based). Based on various arrangements of the cells, widespread range of QCA logic gates and circuits are realizable [4], [10], [12], [21], [22], [23], [24].
Full adder is one of the most frequently utilized components in arithmetic units. In addition to its regular usage (addition), it is employed in other arithmetic operations like subtraction, division, and multiplication. For instance, multiplication could be implemented using successive additions. Hence, designing efficient QCA full adders is a key issue in QCA arithmetic circuitry [5], [6], [8], [13], [17].
Although power consumption is low in QCA technology, constructing QCA logic gates and circuits with lower power consumption has gained more importance recently. In order to measure this factor in QCA, we employ QCAPro tool [7]. For the first time, a QCA power dissipation model was proposed by Timler and Lent in [4] by which average power dissipation of a typical QCA circuit is divided into two major components, “leakage” and “switching”. Power losses throughout clock vacillations (from low to high or high to low) is posited as leakage power and power losses during switching period is considered as switching power [7], [18].
In this paper, we propose an efficient QCA design for three-input XOR gate using explicit interactions between QCA cells ignoring the conventional designing methods. In order to show the suitable functionality of the presented XOR gate, a full adder is constructed based on it and to depict the structural and energy efficiency of the presented full adder cell in comparison to state-of-the-art designs, comprehensive investigations are performed.
The rest of this paper is organized as follows. In Section 2 a review of QCA and some previously offered descriptions for full adder is presented. The novel three-input Exclusive-OR (XOR) gate is proposed in Section 3. In Section 4, we construct a new QCA full adder cell based on the XOR gate and the related results and also the structural and energy dissipation evaluation are demonstrated. Finally Section 5 concludes the paper.
Section snippets
QCA cell
QCA circuits are composed of identical components which are referred to as QCA cells. A QCA cell, a square-shape structure, has four quantum-dots positioned at the four corners and two electrons which are allowed to move between the dots. Due to Coulombic repulsion, the electrons occupy the dots located at the diagonally opposed corners. Hence, two stable states occur which are assigned to logics “0” and “1” [8], [9]. Fig. 1 shows a QCA cell and the two possible polarizations. By placing QCA
Designing efficient three-input exclusive-OR gate
A three-input Exclusive-OR (XOR) gate is one of the most challenging gates in QCA area that is usually designed using cascaded two-input XOR gates as shown in Fig. 6. In this way, the QCA implementation of two-input XOR gate has a crucial role in overall circuit performance. Hence, several implementations for this gate have been made aiming to reduce circuit complexity and latency using diverse cell configuration and wire crossing methods. However, the authors of [13] have proposed a new design
Designing method
In this section, we are going to present a new QCA implementation for full adder cell. As shown in Fig. 9(a), the basic logical diagram for implementing QCA full adder cell is composed of two main components, a three-input majority gate, and a TIEO block. To procure a highly integrated QCA layout, the conventional wire crossing method is employed. In Fig. 9(b), two types of cells are shown where S represents Standard QCA cell and R represents Rotated QCA cells. The fundamental architecture and
Conclusion
In this paper, a new QCA structure for three-input Exclusive-OR is proposed. Unlike previously reported designs which all are majority gate based, this gate uses explicit interactions of cells to procure correct functioning. As shown by results, the proposed XOR gate has yielded significant improvements in terms of latency, area, and cell count. Considering the proposed XOR gate as the main building block, a new well-optimized QCA structure for full adder is presented. The QCA full adder is
Firdous Ahmad received his B.Sc. in Non-Medical from S.P College, Srinagar, India in 2003, his M.Sc. in Electronic Science from Kashmir University, Hazratbal Srinagar, India in 2006 and also received his M.Phil degree award in QCA from Kashmir University, Hazratbal Srinagar, India in 2014. He is currently a Ph.D research scholar of Nanotechnology Laboratory from Kashmir University, Hazratbal Srinagar, India. His research interests include Device Simulation, CNTs, FinFETs, and Nanoelectronics
References (24)
- et al.
Towards modular design of reliable quantum-dot cellular automata logic circuit using multiplexers
Comput. Electr. Eng.
(2015) - et al.
Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder
Microelectron. J.
(2015) - et al.
Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata
Microelectron. J.
(2015) - et al.
Designing efficient QCA logical circuits with power dissipation analysis
Microelectron. J.
(2015) - et al.
Designing quantum-dot cellular automata counters with energy consumption analysis
Microprocess. Microsyst.
(2015) - et al.
A new quantum-dot cellular automata full-adder
Microelectron. J.
(2010) - et al.
Towards the hierarchical design of multilayer QCA logic circuit
J. Comput. Sci.
(2015) - et al.
Restoring and non-restoring array divider designs in quantum-dot cellular automata
Inf. Sci.
(2015) - et al.
Quantum cellular automata
Nanotechnology
(1993) - et al.
Power gain and dissipation in quantum dot cellular automata
J. Appl. Phys.
(2002)
Quantum-dot cellular automata adders
Coplanar full adder in quantum-dot cellular automata via clock-zone based crossover
IEEE Trans. Nanotechnol.
Cited by (129)
A novel low-latency ALU in the one-dimensional clock scheme in QCA nanotechnology
2024, European Physical Journal PlusImplementation of digital differentiator and digital integrator using quantum dot cellular automata
2023, Journal of Optics (India)
Firdous Ahmad received his B.Sc. in Non-Medical from S.P College, Srinagar, India in 2003, his M.Sc. in Electronic Science from Kashmir University, Hazratbal Srinagar, India in 2006 and also received his M.Phil degree award in QCA from Kashmir University, Hazratbal Srinagar, India in 2014. He is currently a Ph.D research scholar of Nanotechnology Laboratory from Kashmir University, Hazratbal Srinagar, India. His research interests include Device Simulation, CNTs, FinFETs, and Nanoelectronics with emphasis on QCA.
Ghulam Mohiuddin Bhat obtained his M.Sc. (Electronics) from the University of Kashmir, Srinagar (India) in 1987, M.Tech. (Electronics) from Aligarh Muslim University (AMU), Aligarh (India) in 1993 and Ph.D. Electronics Eng. from AMU, Aligarh, India in 1997. The major field of research of Dr. Bhat is Signal Processing Techniques and Secure Message Communication. He has served as LECTURER, READER and now as PROFESSOR & DIRECTOR University Science Instrumentation Centre (USIC), University of Kashmir. He has published many research papers on his area of interest. He has worked in the area of Mobile Radio Communication, Spread Spectrum Communication and Neural Networks, Nanotechnology. His present research interests include Secure Message Communication, Neural networks, Quantum-dot cellular Automata (QCA) and Signal Processing techniques for communication.Prof. Bhat is a member of many scientific bodies and professional societies including India Science congress Association (ISCA), Systems Society of India. Prof Bhat has received two India Patents for two innovative technologies which are under process of commercialization. Prof. Bhat is the Chairman of GIAN Cell-J&K, Advisor EDC and Co-ordinator TUC, at University of Kashmir which are the professional bodies for indigenous technology innovation and technolo-preneurship development in the state of Jammu & Kashmir (India). He is currently Head of Department Electronic Science & IT from Kashmir University and Dean Faculty of Engineering.
Hossein Khademolhosseini received B.Sc. degree in computer engineering in 2008 from Shiraz University, Shiraz, Iran. He also received his M.Sc. degree in computer architecture at Department of Computer Engineering, Science and Research Branch of Islamic Azad University, Tehran, Iran, in 2011. He is currently working toward the Ph.D. degree in computer architecture engineering at the Science and Research Branch of IAU. His research interests are computer arithmetic, photonic NoC and electronics with emphasis on QCA and VLSI.
Saeid Azimi received his B.Sc. degree in Computer Engineering at Islamic Azad University South Tehran Branch in 2013. He started M.Sc. degree in Computer Architecture at Islamic Azad University of Qazvin from 2013. He is research assistant at Computer Engineering, Islamic Azad University of Qazvin, Qazvin, Iran. His research interests include on High Speed Low Power VLSI Circuit Design, Emerging Technologies, mainly on Carbon Nanotube (CNT) and Quantum-dot Cellular Automata (QCA).
Shaahin Angizi received his B.Sc. in computer hardware engineering from South Tehran Branch, IAU, Tehran, Iran in 2012 and his M.Sc. in computer engineering, computer architecture from Science and Research Branch, IAU, Tabriz, Iran in 2014. He is currently a senior research assistant at School of Computer Science of IPM, Tehran, Iran. His research interests include high performance and low power VLSI designs and Nanoelectronics with emphasis on QCA. He is a student member of IEEE.
Keivan Navi received the Ph.D. degree in computer architecture from Paris XI University, Paris, France, in 1995 and the M.Sc. degree in electronics engineering from Sharif University of Technology, Tehran, Iran in 1990. He is currently a Full Professor in Faculty of Electrical and Computer Engineering of Shahid Beheshti University and also a senior member of IEEE. He is in charge of the Nanotechnology and Quantum Computing Laboratory (NQC Lab.). His research interests include Nanoelectronics with emphasis on CNFET, QCA and SET, Computer Arithmetic, Interconnection Network Design and Quantum Computing and cryptography.