Elsevier

Journal of Computational Science

Volume 22, September 2017, Pages 54-68
Journal of Computational Science

Design of novel carry save adder using quantum dot-cellular automata

https://doi.org/10.1016/j.jocs.2017.08.019Get rights and content

Abstract

Complex adder designs in Quantum Dot-Cellular Automata (QCA) are primary focus of researchers on lowering cell-count, delay and QCA gates. The cell count, area and delay of two input adders such as Brent-Kung, Ladner-Ficher, Han-Carlson and Kogg-Stone are at least doubles when three numbers are added, compared to adding two numbers. Besides, the interconnected QCA wires for these adders decrease the addition time. To eliminate this problem, a new 4-bit Carry Save Adder (CSA) is proposed in this paper. To design the CSA circuit, a novel design of full adder circuit using 5-input majority gate (MV) has been proposed. The proposed design has around 11.76% improvement in cell count and 33.33% improvement in latency compared to the existing QCA full-adders. Besides, when three binary numbers are added, CSA is far more advantageous compared to similar addition using two input prefix adders, in terms of QCA cell count, area and clock delay. Compared to 4-bit traditional adders, proposed CSA has around 80% decreases in overall circuit cost. The QCA layout of CSA is the first one of its kind. An improved QCA layout of a 4-bit ripple carry adder (RCA) is also proposed in this paper. The RCA has around 7.6% improvement in cell count, 33.33% improvement in latency and around 5.56% improvement in overall cost over compared to the existing layouts.

Introduction

Integrated circuits with Complementary Metal Oxide Semiconductor (CMOS) technology are being developed by scaling down transistor size. In 1993C. S. Lent first proposed Quantum-Dot Cellular Automata (QCA), which takes advantage of quantum mechanical effects to implement logic device at nano-scale [1]. QCA cell was fabricated first by Amlani et al. by using materials GaAs [2]. Then several efforts have been made to explore the experimental demonstration to manufacture QCA [3], [4], [5]. In the year 2014, Electrostatic QCA has been fabricated successfully on Si 〈100〉 at room temperature by DiLabio et al. [6]. The QCA fabricated by creating controllable dangling bonds on Si substrate. The fabricated QCA [6] can function at least to temperature of 293 K. Processing speed at THz frequency, low power consumption and high device density, are some of the advantages of QCA technology. Besides it offers a new computational method for processing information. In place of voltage levels, as in CMOS technology, logic state of digital circuits, are achieved by the polarization of electrons.

QCA layouts of arithmetic and logical circuits are of research interest. A number of studies and researches have been achieved that suggest QCA layouts of various types of adders [7] such as ripple carry adder (RCA), carry look ahead adder (CLA), Brent Kung adder, and Kogg Stone adder. All of these are two input n-bit adders. But addition of more than two numbers is often required in binary multiplication. Binary multiplication is performed by multi-operand adders in the following steps:

  • To add the partial products.

  • Computing vector inner products.

  • Computing averages e.g. mean filter design.

Such multi-operand addition is explained in [8]. This can be achieved either by the serial implementation of multi-operand addition or by the parallel addition using adder trees.

Using fast prefix adders, the order of the magnitude of propagation time for serial addition of k n-bit binary numbers is given as:Tserialmultiadd=O(Klog(n+logk))=O(klogn+klog(logk))

Thus, time required during addition grows super linearly with k when n is fixed. Otherwise, the time grows logarithmically with n for a given k. Again, the order of the magnitude of propagation time for parallel multi-operand addition by prefix adder trees and ripple carry adder trees are given in [8] respectively asTtree-fast-multi-add= O(log n+ log(n+1)+...+ log(n+log2k1))=O(logklog n+ logklog logk)Ttree-ripple-multi-add=O(n+(n+1)+...+(n+ log2k1))= O(n+ logk)

In case of prefix adders, the addition of the previous stage needs to be completed before the start of the next stage. The block diagram of 3-input n-bit adder is shown in Fig. 1(a). The case of addition of three n-bit numbers using a two input n-bit adder is illustrated in Fig. 1 (b). In Fig. 1, A, B and C are the three inputs. SUM is the addition value corresponding to the inputs A, B and C. In Fig. 1(a), the three inputs are directly added and the corresponding sum is produced. On the other hand, in Fig. 1(b), two input n-bit adders are cascaded with an interconnected line. First, the inputs A and B are added. The resultant value is then used as an input to the next adder where it is added with input C and the final sum is generated. Thus in case of prefix adders, whose QCA layouts are already available [7] cell count, area and latency becomes more than the double, for addition of three numbers. This is because in a QCA layout, interconnects are formed by QCA cells that needs to be provided with clocking zones. Thus, it can be concluded that prefix adders are advantageous when sizes of the operands are large, i.e., when n becomes larger. In this paper the QCA architecture of a three input 4-bit CSA and four input 4-bit CSA are proposed.

The orientation of this work is as follows. In Section 2, the contribution of the article is outlined. Section 3 presents an overview of QCA. An improved QCA layout of a full adder has been proposed in Section 4. The QCA layout of a 4-bit RCA using five input majority gate (MV) is proposed in Section 5. Section 6 describes the QCA design technique of CSA to perform addition of three 4-bit numbers and four 4-bit numbers. In Section 7, the QCA layouts of the full adder, 4-bit RCA, three input 4-bit CSA and four input 4-bit CSA are described. The simulation results of the layouts are also explained in this section. Further the comparative studies of the proposed full adder, RCA circuit and CSA circuit with previously proposed layouts have been performed in Section 8. The complexity i.e. cell count, area, latency and quantum cost of the proposed layouts is also described in this section. In Section 8, the advantage of CSA layout is also clearly explained. Finally Section 9 concludes the report.

Section snippets

Contributions of the article

This article have the contributions are as follows.

QCA cell

A QCA cell [16], [17], [18], [19] with four quantum dots is shown in Fig. 2. The dots are loaded with two extra electrons. The electrons can tunnel to one of the two quantum dots adjacent to their position. They cannot tunnel outside the boundary of the cell. Two possible polarizations can be produced due to columbic effect, i.e., P = +1 and P = −1. This arrangement is described in Fig. 2(a) and (b). Here, P stands for cell polarization. P = +1 encodes the logic “1” and P = –1 as logic “0” [20], [21],

QCA full adder

An improved layout of a 1-bit full adder based on 3-input MV and 5-input MV and an inverter has been proposed in this section. The full adder layout proposed in this paper improves the QCA layout in terms of latency and cell count compared to that already has been proposed in [9], [10] and [34], [35]. Five inputs MV based QCA schematic diagram of one-bit full adder is shown in Fig. 6(a). It can be seen from Fig. 6(a) that the carry out Cout is generated using a 3 input majority gate. The addend

Ripple carry adder design in QCA

The QCA design of a 4-bit RCA using 5-input and 3-input MVs is proposed in this section. This design outshines the earlier design of QCA based RCA [7] in terms of delay and cell count. The MV schematic diagram of RCA is shown in Fig. 7. Since the 4-bit RCA requires cascading of four full adders each of which requires one five input and one three input majority gate. The same D-latch convention given in [11] is used to represent the MV diagram of Fig. 7. The full adder design of Section 4

Carry save adder in QCA

Two operand adders are required to be cascaded to add more than two n-bit numbers. But the propagation delay introduced in such a process is huge, as already discussed in Section 1. The advantage of carry save addition is also discussed. The implementation of carry save addition to add three numbers and four numbers both are discussed in this section. The carry save addition technique is described in [37], [38]. CSA is a three-input adder. It requires one two input adder to complete the

QCA layout design of full adder, ripple carry adder and carry save adders

The QCA layout design with simulation results of full adder and the RCA and finally the three inputs CSA and four inputs CSA are presented in this section. The designing of the layouts and their simulations are achieved using the QCADesigner tool [28].

Comparison of proposed full adder with prior works

Table 3 represents the cell count, area, latency i.e. the number of clock cycles and the overall cost of the proposed full adder layout. The Table 3 also presents the comparison between proposed layout and previous layouts of full adders reported in [9], [10], [11], [12] as these works appear to present the latest available designs. The cost function is given in [29] asOverall Cost = Area × Latency2

In [9], two types of full adder, i.e. robust and non-robust full adder have been explored. Both these

Conclusion

Carry save addition technique is used to add more than two n-bit binary numbers. The CSA implemented in this paper can add up to four 4-bit numbers. For adding larger number of operands, the proposed CSA can be cascaded to form an adder tree. This addition technique is much faster than adding the same number of operands by cascading other adders like RCA, Brent-Kung adder, Landler fisher adder, etc. This paper proposed a novel layout of full adder using 5-input MV. The proposed layout has

Dr. Debashis De received M.Tech degree in Radio Physics & Electronics in 2002. He obtained his Ph.D (Engineering) from Jadavpur University in 2005. He worked as R & D Engineer of Telektronics. Presently he is an Associate Professor in the Department of Computer Science and Engineering of West Bengal University of Technology, India and Adjunct Research Fellow of University of Western Australia, Australia. He was awarded the prestigious Boyscast Fellowship by department of Science and Technology,

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    Dr. Debashis De received M.Tech degree in Radio Physics & Electronics in 2002. He obtained his Ph.D (Engineering) from Jadavpur University in 2005. He worked as R & D Engineer of Telektronics. Presently he is an Associate Professor in the Department of Computer Science and Engineering of West Bengal University of Technology, India and Adjunct Research Fellow of University of Western Australia, Australia. He was awarded the prestigious Boyscast Fellowship by department of Science and Technology, Govt. of India to work at Herriot-Watt University, Scotland, UK. He is also awarded Endeavour Fellowship Award during 2008–2009 by DEST Australia to work in the University of Western Australia. He received Young Scientist award both in 2005 at New Delhi and in 2011 at Istanbul by International Union of Radio Science, H.Q., Belgium. His research Interest includes Location Management and Power Consumption Control in Mobile network and low power Nano device design for mobile application and disaster management. His email id: [email protected].

    Jadav Chandra Das received M.Tech degree in Multimedia and Software Systems from West Bengal University of Technology, West Bengal, India, in 2011. Presently he is an Assistant Professor in the Department of Computer Science and Engineering, Swami Vivekananda Institute of Science and Technology under West Bengal University of Technology, Kolkata, India. His research interest includes Image Processing, Cryptography and QCA based Image Processing. His email id: [email protected].

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