A general methodology for direction-based irregular routing algorithms

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Abstract

This paper presents a general methodology for generating deadlock-free routing algorithms for irregular networks. Constructing a spanning tree on the given network, assigning directions to the network channels, creating deadlock-free zones, and specifying a logical sequence of the produced deadlock-free zones are the four fundamental steps that the proposed methodology takes to generate deadlock-free and connected routing algorithms. By applying the proposed methodology with two known labeling methods we have generated six irregular routing algorithms: three of them are novel routing algorithms and three of them (the Up/Down, Left/Right, and L-turn routing algorithms) have already been proposed in the literature. Extensive simulation experiments have been performed considering various network topologies, different network sizes (considering different network nodes and network channels), various message lengths, a variety of spanning tree roots, and a wide range of message (traffic) generation rates. Simulation results show that the six routing algorithms can be divided into three pairs. Routing members of each pair show similar behavior in terms of message latencies and saturation generation rates. However, it is worth noting that for a given topology the performance of the six routing algorithms may be totally different and it mainly depends on the network topology.

Introduction

Irregular networks have emerged as one of the cost-effective alternatives for high performance parallel computing in a wide range of systems, from on-chip systems (SoCs) [4] to networks of workstations (NOWs) [15], [3]. In such systems, an irregular high speed network is often required in order to provide the wiring flexibility needed in the network and also the design of scalable systems with incremental expansion capability.

Without a careful design for the routing scheme in irregular networks, deadlock may occur. Since the topology of such networks is not definite, designing deadlock-free routing algorithms is usually done without any pre-assumption about the network topology. Moreover, as the name irregular implies, there is no a mathematical relation between network nodes and channels. Therefore, the major problem of these networks is the complexity of designing a deadlock-free routing algorithm. On the other hand, for regular networks, since there is a mathematical relation between network nodes and channels, designing routing algorithms is rather straightforward. Indeed, this mathematical relation helps the designers to develop simple and efficient distributed routing algorithms.

Many routing algorithms have been reported in the literature for irregular topologies. In order to clarify the area on which this work is based we classify the previously proposed routing algorithms into two different groups: (1) routing algorithms based on the loop-free assignment of directions to the operational channels (node and channel indexing) and (2) virtual channel-based routing algorithms.

Examples of the first group are up/down routing [14], prefix routing [16], left/right routing [6], L-turn routing [6] and the effective methodology proposed in [13] to improve the performance of the up*/down* routing. The second group includes layered routing [7] and the recent routing algorithm proposed in [12]. Duato’s methodology [2], [3], which is applied to irregular networks, lies in the second group [15].

The proposed methodology in this paper resides in the first group as it uses the channel direction in generating deadlock-free routing algorithms. The methodology, in addition to providing a novel approach to construct routing algorithms, reveals the relation between the previously reported routing algorithms proposed in different studies.

The switching technique we use in this paper is wormhole switching, which is used to build irregular networks such as Myrinet [1] and ServerNet [5]. However, the design methodologies proposed in this paper are also valid for packet switching and virtual cut-through.

The rest of the paper is organized as follows. Section 2 describes the basic steps to prepare the topology in order to deal with the proposed methodology, and also presents the preliminary definitions used in the rest of the paper. Our comprehensive approach to generate deadlock-free routing algorithms is proposed in Section 3. Section 4 presents the experimental performance results for the routing algorithms obtained by the methodology. Finally, Section 5 concludes this paper and outlines some directions for future work.

Section snippets

Preliminaries and basic definitions

In order to apply the new methodology to an irregular network, first we divide the network channels into four types or directions as done in [6]. These directions are based on the combination of vertical (Up and Down) and horizontal (Left and Right) directions. In other words, each channel is labeled by two directions, a vertical and a horizontal direction (Fig. 1), for example Up-Right channel.

Assigning directions to the channels are done as follows. An arbitrary spanning tree is constructed

The proposed methodology

The proposed methodology uses the following steps to generate connected and deadlock-free routing algorithms.

Step 1. Assigning directions to the network channels by constructing a spanning tree and pre-order traversal of the constructed spanning tree.

Step 2. Determining deadlock-free zones according to Theorem 1.

Step 3. Placing the generated deadlock-free zones according to Corollary 1 in a sequence that leads to a connected routing algorithm.

In brief, the first step assigns directions to the

Performance evaluation

To evaluate the functionality of the routing algorithms generated by the proposed methodology a discrete-event simulator operating at flit level has been developed [11]. The measure of interest is the average message latency (the average amount of time a message takes to reach its destination and completely be consumed). However, some assumptions were made when developing the simulation scenarios, as follows: (a) The destination of a message is randomly chosen among the other network nodes; (b)

Conclusions

We have proposed a methodology to generate deadlock-free routing algorithms for irregular networks. One of the advantages of the proposed methodology is that it covers three well-known previously reported routing algorithms (the Up/Down, Left/Right, and L-turn routing algorithms) and reveals the implicit relation between them. Also, three new routing algorithms were introduced as some attractive alternatives to the previous ones. As indicated by simulation results, the six routing algorithms

R. Moraveji is currently a Ph.D. student in the Centre of Distributed and High Performance Computing, School of Information Technologies, The University of Sydney, Australia. Reza received his B.Sc. and M.Sc. degrees, both in electrical and computer engineering, from Shahid Beheshti University, Tehran, Iran, in 2004 and 2007, respectively. He worked as a research assistant at IPM (Institute for Studies in Theoretical Physics and Mathematics), School of Computer Science, Tehran, Iran, during the

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R. Moraveji is currently a Ph.D. student in the Centre of Distributed and High Performance Computing, School of Information Technologies, The University of Sydney, Australia. Reza received his B.Sc. and M.Sc. degrees, both in electrical and computer engineering, from Shahid Beheshti University, Tehran, Iran, in 2004 and 2007, respectively. He worked as a research assistant at IPM (Institute for Studies in Theoretical Physics and Mathematics), School of Computer Science, Tehran, Iran, during the period 2005–2008. During the same time he was a member of the HPCAN (high performance computing architectures and networking) research group at the department of computer engineering at Sharif University of Technology, Tehran, Iran (2006–2008). His current research interests are cloud computing, distributed programming models (MapReduce, Dryad, etc.), distributed file systems, Hadoop, and low power system design.

H. Sarbazi-Azad received his B.Sc. degree in electrical and computer engineering from Shahid-Beheshti University, Tehran, Iran, in 1992, his M.Sc. degree in computer engineering from Sharif University of Technology, Tehran, Iran, in 1994, and his Ph.D. degree in computing science from the University of Glasgow, Glasgow, UK, in 2002. He is currently associate professor of computer engineering at Sharif University of Technology, and heads the School of Computer Science of the Institute for Studies in Theoretical Physics and Mathematics (IPM), Tehran, Iran. His research interests include high performance computer architectures, NoCs and SoCs, parallel and distributed systems, performance modeling/evaluation, graph theory and combinatorics, and wireless/mobile networks, on which he has published more than 200 refereed conference and journal papers. He received the Khwarizmi International Award in 2006, and the TWAS Young Scientist Award in engineering sciences in 2007. He is a member of managing board of the Computer Society of Iran (CSI), and has served as the editor-in-chief for the CSI Journal on Computer Science and Engineering since 2005. He is an editorial board member and has been guest editor for several special issues on high performance computing architectures and networks (HPCAN) in related journals. Dr Sarbazi-Azad is a member of ACM.

A.Y. Zomaya is currently the Chair Professor of High Performance Computing and Networking in the School of Information Technologies, The University of Sydney. He is also the Director for the newly established Sydney University Centre for Distributed and High Performance Computing. Prior to joining Sydney University he was a Full Professor in the Electrical and Electronic Engineering Department at the University of Western Australia, where he also led the Parallel Computing Research Laboratory during the period 1990–2002. He is the author/co-author of seven books, more than 350 publications in technical journals and conferences, and the editor of eight books and eight conference volumes. He is currently an associate editor for 16 journals, the Founding Editor of the Wiley Book Series on Parallel and Distributed Computing and a Founding Co-Editor of the Wiley Book Series on Bioinformatics. Professor Zomaya was the Chair of the IEEE Technical Committee on Parallel Processing (1999–2003) and currently serves on its executive committee. He also serves on the Advisory Board of the IEEE Technical Committee on Scalable Computing and IEEE Systems, Man, and Cybernetics Society Technical Committee on Self-Organization and Cybernetics for Informatics and is a Scientific Council Member of the Institute for Computer Sciences, Social–Informatics, and Telecommunications Engineering (in Brussels). He received the 1997 Edgeworth David Medal from the Royal Society of New South Wales for outstanding contributions to Australian Science. Professor Zomaya is also the recipient of the Meritorious Service Award (in 2000) and the Golden Core Recognition (in 2006), both from the IEEE Computer Society. He is a Chartered Engineer (CEng), a Fellow of the American Association for the Advancement of Science, the IEEE, the Institution of Engineering and Technology (UK), and a Distinguished Engineer of the ACM. His research interests are in the areas of high performance computing, parallel algorithms, mobile computing, and bioinformatics.

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