A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms

Abstract

Networks-on-Chip (NoCs) can be used for test data transportation during manufacturing tests. On one hand, NoC can avoid dedicated Test Access Mechanisms (TAMs), reducing long global wires, and potentially simplifying the layout. On the other hand, (a) it is not known how much wiring is saved by reusing NoCs as TAMs, (b) the impact of reuse-based approaches on test time is not clear, and (c) a computer aided test tool must be able to support different types of NoC designs. This paper presents a test environment where the designer can quickly evaluate wiring and test time for different test architectures. Moreover, this paper presents a new test scheduling algorithm for NoC TAMs which does not require any NoC timing detail and it can easily model NoCs of different topologies. The experimental results evaluate the proposed algorithm for NoC TAMs with an exiting algorithm for dedicated TAMs. The results demonstrate that, on average, 24% (up to 58%) of the total global wires can be eliminated if dedicated TAMs are not used. Considering the reduced amount of dedicated test resources with NoC TAM, the test time of NoC TAM is only, on average, 3.88% longer compared to dedicated TAMs.

Introduction

With the scaling of microchip technology, computation is becoming cheaper than communication. The main reason is that global wires do not scale as transistors and local wires [13] because they communicate across the chip. Global wires can be found in the chip-level communication infra-structures like buses and Networks-on-Chip (NoCs). NoCs [4] may replace global buses in the near future due to scalability, parallel communication features, and shorter global wires.

Modular testing has been proposed as a solution to test such complex SoCs [12]. The conceptual model for modular testing consists of test wrappers (used to switch between functional and test modes), test sources and sinks (used, respectively, to generate test stimuli and to compare the actual test responses to the expected responses), and Test Access Mechanisms (TAMs) (used to transport test data from/to the test pins to/from the Core-Under-Test (CUT)). The most common practice for TAM design is to include dedicated and global test buses used only for test data transportation. Since these TAMs consist of long global wires, dedicated test buses are also subject to the same interconnect problems such as signal integrity, delay, and power dissipation. In an attempt to avoid the long global wires related to the TAMs, Cota et al. [9] proposed the use of the NoC to transport test data, avoiding long global wires both in functional and in test modes.

The main motivation to use a NoC as TAM is to avoid the extra long global wires required to implement the dedicated TAMs. It has several potential benefits like reducing area (wiring area and buffers), layout congestion, and power dissipation over long wires with buffers. Additional motivation includes the large internal bandwidth of NoCs that can be used to optimize the test time and the support for globally asynchronous and locally synchronous systems. Testing systems with multiple clocks is a noticeable design challenge. The use of this type of NoC as TAM, which is an open research topic, could simplify the test data transportation for systems with multiples clocks or asynchronous systems.

The original contributions of this paper consist of an adaptable test scheduling algorithm for NoC TAM, a test environment used to quickly evaluate different test architectures, and a method to estimate the wire length required by dedicated TAMs. This paper proposes a new test scheduling algorithm for test architecture based on NoC TAM that requires only topology and channel bandwidth information of the NoC. This feature eases the modeling of other NoCs, for example, with different topologies, where most NoC reuse approaches existing so far are specific for mesh-based NoCs. The test environment has been built to ease the generation and analysis of results. It consists of a set of NoC-based SoCs used as benchmarks, scripts to automate the execution and analysis of hundreds of cases, the proposed test scheduling for NoC TAM, a conventional test scheduling approach used for comparison, and the proposed wire length estimation method. As far as we know, this environment is the first to support both NoC-based and dedicated TAMs test architectures and is the first to numerically evaluate the wire length of dedicated TAMs. This type of environment is important because, as demonstrated in the results, both test architectures have advantages and drawbacks, thus, the designer needs an environment like this to quickly evaluate and select the most appropriate solution.

This paper is organized as follows. Section 2 summarizes the basic concepts of SoC testing for dedicated TAMs and presents an example of a test scheduling algorithm. The proposed test architecture for NoC TAM is introduced in Section 3. Section 4 presents previous papers about test scheduling for NoC TAM and compares them with the proposed approach. Section 5 presents the proposed wire length estimation method, motivating the use of the existing NoC as TAM. Section 6 presents the proposed test scheduling for NoC TAMs. Section 7 presents four sets of experiments: wire length, test time when the NoC is faster than tester, test time when the NoC is as fast as the tester, and test time for several NoC topologies. Section 8 presents the conclusion of the paper.