Energy and time constrained task scheduling on multiprocessor computers with discrete speed levels

https://doi.org/10.1016/j.jpdc.2016.02.006Get rights and content

Highlights

  • Address energy and time constrained task scheduling with discrete speed levels.

  • Prove the NP-hardness even on a uniprocessor computer with only two speed levels.

  • Develop algorithms with two components: task scheduling and speed determination.

  • Derive worst-case asymptotic performance bounds and average-case asymptotic per- formance bounds.

  • Perform extensive simulations to verify the analytical results.

Abstract

Energy and time constrained task scheduling on multiprocessor computers with discrete clock frequency and supply voltage and execution speed and power levels is addressed as combinatorial optimization problems. It is proved that the problem of minimizing schedule length with energy consumption constraint and the problem of minimizing energy consumption with schedule length constraint are NP-hard even on a uniprocessor computer with only two speed levels. A class of algorithms is developed to solve the above two problems. These algorithms include two components, namely, a list scheduling algorithm for task scheduling and a list placement algorithm for speed determination. A worst-case asymptotic performance bound and an average-case asymptotic performance bound are derived for our algorithms on uniprocessor computers, and a worst-case asymptotic performance bound is derived for our algorithms on multiprocessor computers. Extensive simulations are performed to verify our analytical results. It is found that our algorithms produce solutions very close to optimal and are practically very useful.

Introduction

Modern high-performance processors can consume significant amount of energy. An idle processor (e.g., Intel Core i7-975 3.33 GHz, DDR3-1066, 1 MB L2, 8 MB L3) may require 83 W of power. The peak power consumption can be as high as 210 W (e.g., AMD FX 8350 4.0 GHz, DDR3-1866, 8 MB L2, 8 MB L3)  [36]. As the scale of multi-core and many-core systems increases to the order of 106 cores, the power consumption also increases dramatically. As of June 2015, the average power of the worlds ten fastest supercomputers is 6.4454 MW  [37], costing 56,461,704 kWh of electricity and 6,137,387 USD (assuming 10.87 cents per Kilowatthour [34]) per year. On July 29, 2015, President Obama signed an executive order—creating a National Strategic Computing Initiative with the objective of accelerating delivery of a capable exascale computing system, which is able to perform a quintillion, i.e., 1018, floating point operations per second  [38]. Since it is widely believed that power consumption of any computing system should not exceed 20 MW, we are facing the challenge of developing an exascale system with 50,000 MFLOPS/Watt; however, the current (as of June 2015) technology can only achieve 7031.58 MFLOPS/Watt  [35]. Therefore, energy efficiency is listed as the number one challenge of the top ten exascale system research challenges  [33].

According to Moore’s law, power consumption in computer systems has increased at an exponential speed for decades  [31]. Power density in high-performance computer systems will soon reach that of a nuclear reactor  [79]. Such increased energy consumption causes severe economic, ecological, and technical problems  [17], [20], [25], [75]. Power conservation is critical in many computation and communication environments and has attracted extensive research activities. Reducing processor energy consumption has been an important and pressing research issue in recent years. There has been increasing interest and importance in developing high-performance and energy-efficient computing systems  [16], [18], [19]. There exists an explosive body of literature on power-aware computing and communication. The reader is referred to  [1], [8], [9], [77], [78], [79], [91] for comprehensive surveys.

Power consumption in computing systems can be reduced by thermal-aware hardware and software design at various levels. Software techniques for power reduction are supported by a mechanism called dynamic voltage scaling (equivalently, dynamic frequency scaling, dynamic speed scaling, dynamic power scaling)  [28]. A power-aware algorithm can change supply voltage and frequency at appropriate times to optimize a combined consideration of performance and energy consumption. There are many existing technologies and commercial processors that support dynamic voltage (frequency, speed, power) scaling  [29], [30], [32].

Dynamic power management at the operating system level refers to supply voltage and clock frequency adjustment schemes implemented while tasks are running. These energy conservation techniques explore the opportunities for tuning the energy-delay tradeoff  [76]. Since the pioneering work in  [80], [82], power-aware task scheduling on processors with variable voltages and speeds has been extensively studied, including scheduling tasks with arrival times and deadlines on a uniprocessor computer with minimum energy consumption  [4], [5], [6], [12], [42], [45], [57], [60], [59], [83], scheduling independent or precedence constrained tasks on uniprocessor or multiprocessor computers in real-time applications  [3], [23], [26], [27], [40], [44], [46], [61], [63], [66], [70], [71], [73], [74], [81], [87], [88], [89], [90], dealing with the energy-delay tradeoff  [7], [11], [14], [22], [43], [48], [58], [72], [86], [92], developing high-performance and energy-efficient computing systems  [10], [16], [18], [19], improving system level power management  [15], [39], [47], [62], [67], and conducting other studies  [2], [65], [68], [85]. In  [50], [52], [54], [53], [51], [55], [56], we addressed energy and time constrained power allocation and task scheduling on multiprocessors with dynamically variable voltage and frequency and speed and power as combinatorial optimization problems.

Much existing research assume that a task can be supplied with any power and a processor can be set at any speed, that is, clock frequency and supply voltage and execution speed and power supply can be changed continuously in any range. However, the currently available processors have only a few discrete clock frequency and supply voltage and execution speed and power levels  [41], [69]. Much existing research also assume that clock frequency and supply voltage and execution speed and power supply can be changed in any range. However, discrete settings also imply that clock frequency and supply voltage and execution speed and power supply can only be change in certain bounded range. The constraints of discrete and bounded settings certainly make our optimization problems more difficult to solve. However, power-aware task scheduling algorithms developed with such constraints, though more complicated, will be more practically useful.

Task scheduling on processors with discrete speed levels has been investigated by a number of researchers. For instances, it was shown that an optimal preemptive schedule with minimum energy consumption on a uniprocessor computer can be found in polynomial time  [45], [60], [59]. Processors with discrete speed levels were also considered in real-time multiprocessor systems  [64], [88]. However, to the best of the author’s knowledge, energy and time constrained nonpreemptive task scheduling on multiprocessor computers with discrete speed levels has not been well studied analytically, although experimental studies have been conducted by many researchers. The motivation of this paper is to make investigation towards this direction. We find that addressing discrete and bounded speed levels simultaneously does not yield analytically tractable algorithms and manageable and meaningful results. Therefore, we will concentrate on discrete speed levels which are assumed to be enough to accommodate the needs of our algorithms.

The main contributions of the present paper are as follows. First, we prove that the problem of minimizing schedule length with energy consumption constraint and the problem of minimizing energy consumption with schedule length constraint are NP-hard even on a uniprocessor computer with only two speed levels (Proposition 1 in Section  3.1 and Proposition 2 in 4.1). Second, we develop a class of algorithms to solve the above two problems. These algorithms include two components, namely, a list scheduling algorithm for task scheduling and a list placement algorithm for speed determination (Sections  3.2 Scheduling on multiprocessor computers, 4.2 Scheduling on multiprocessor computers). Third, we derive a worst-case asymptotic performance bound and an average-case asymptotic performance bound for our algorithms on uniprocessor computers (Theorem 1 and Corollary 1 in Section  3.1 and Theorem 3 and Corollary 2 in Section  4.1), and a worst-case asymptotic performance bound on multiprocessor computers (Theorem 2 in Section  3.2 and Theorem 4 in Section  4.2). Fourth, we perform extensive simulations to verify our analytical results. We found that our algorithms produce solutions very close to optimal and are practically very useful (Section  5).

Section snippets

The model of power consumption

Power dissipation and circuit delay in digital CMOS circuits can be accurately modeled by simple equations, even for complex microprocessor circuits. CMOS circuits have dynamic, static, and short-circuit power dissipation; however, the dominant component in a well designed circuit is dynamic power consumption p (i.e., the switching component of power), which is approximately p=aCV2f, where a is an activity factor, C is the loading capacitance, V is the supply voltage, and f is the clock

Energy constrained scheduling

Given n tasks with task execution requirements r1,r2,,rn, the problem of minimizing schedule length with energy consumption constraint E on a multiprocessor computer with m processors is to determine the execution speeds sj1,sj2,,sjn and a nonpreemptive schedule of the n tasks on the m processors such that the schedule length is minimized and the total energy consumed does not exceed E.

Time constrained scheduling

Given n tasks with task execution requirements r1,r2,,rn, the problem of minimizing energy consumption with schedule length constraint T on a multiprocessor computer with m processors is to determine the execution speeds sj1,sj2,,sjn and a nonpreemptive schedule of the n tasks on the m processors such that the total energy consumption is minimized and the schedule length does not exceed T.

Simulation results

In this section, we present simulation results for the nine algorithms developed in this paper, which are SRF-SOF, SRF-LP, SRF-LOF, LS-SOF, LS-LP, LS-LOF, LRF-SOF, LRF-LP, and LRF-LOF. Our experimental performance evaluation is based on two performance measures, namely, normalized schedule length and normalized energy consumption.

The normalized schedule length NSLA of an algorithm A that solves the problem of minimizing schedule length with energy consumption constraint is defined as NSLA=TA((m/

Concluding remarks

We have addressed energy and time constrained task scheduling on multiprocessor computers with discrete clock frequency and supply voltage and execution speed and power levels. We considered the problem of minimizing schedule length with energy consumption constraint and the problem of minimizing energy consumption with schedule length constraint. We proved that both problems are NP-hard even on a uniprocessor computer with only two speed levels. We developed a type of algorithms to solve the

Keqin Li is a SUNY Distinguished Professor of computer science in the State University of New York. He is also a Distinguished Professor of Chinese National Recruitment Program of Global Experts (1000 Plan) at Hunan University, China. He was an Intellectual Ventures endowed visiting chair professor at the National Laboratory for Information Science and Technology, Tsinghua University, Beijing, China, during 2011–2014. His current research interests include parallel computing and

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    Keqin Li is a SUNY Distinguished Professor of computer science in the State University of New York. He is also a Distinguished Professor of Chinese National Recruitment Program of Global Experts (1000 Plan) at Hunan University, China. He was an Intellectual Ventures endowed visiting chair professor at the National Laboratory for Information Science and Technology, Tsinghua University, Beijing, China, during 2011–2014. His current research interests include parallel computing and high-performance computing, distributed computing, energy-efficient computing and communication, heterogeneous computing systems, cloud computing, big data computing, CPU–GPU hybrid and cooperative computing, multicore computing, storage and file systems, wireless communication networks, sensor networks, peer-to-peer file sharing systems, mobile computing, service computing, Internet of things and cyber–physical systems. He has published over 400 journal articles, book chapters, and refereed conference papers, and has received several best paper awards. He is currently or has served on the editorial boards of IEEE Transactions on Parallel and Distributed Systems, IEEE Transactions on Computers, IEEE Transactions on Cloud Computing, Journal of Parallel and Distributed Computing, International Journal of Parallel, Emergent and Distributed Systems, International Journal of High Performance Computing and Networking, Optimization Letters, and International Journal of Big Data Intelligence. He is an IEEE Fellow.

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