Simulation of NoC power-gating: Requirements, optimizations, and the Agate simulator

Highlights

• Key requirements of NoC power-gating simulation regarding accuracy, efficiency, full-system compatibility, extensibility and flexibility are identified.

• Insights on the problems, solutions and optimizations generally applicable to NoC power-gating simulation platforms are provided.

• A cycle-accurate simulator that facilitates research on NoC router power-gating is proposed.

Abstract

The static power consumption of networks-on-chip (NoCs) has been increasing across each technology generation. Power-gating is a very promising approach that can dramatically reduce NoC static power but may potentially cause substantial performance penalty. Significant research is needed to explore effective ways of applying power-gating to NoC routers. To enable further research advancement, cycle-accurate NoC power-gating simulation infrastructure is much needed. In this work, we identify key requirements for NoC power-gating simulation and discuss three important optimizations that can enable such simulators to handle router pipeline draining and handshaking correctly and efficiently. We also propose Agate, an effective NoC power-gating simulator that satisfies the key requirements and optimizations. It can be integrated into Gem5 for closed-loop, full-system simulation of NoC-based many-core computing systems. We demonstrate the capability of Agate by simulating and evaluating several power-gating schemes, including the recently proposed Power Punch power-gating scheme.

Introduction

With an increasing number of cores integrated on a chip, networks-on-chip (NoCs) have been adopted as the de facto architecture for current and future many-core processors. While NoCs provide a more scalable interconnection solution compared with traditional buses and point-to-point interconnects, the added complexities of buffers, crossbars and various control logic in the NoC greatly increase its power demand. Industrial and research chips have shown that NoCs can draw a substantial percentage of the overall chip power (e.g., 17% in Niagara  [17], 19% in SCORPIO  [9], and 28% in Intel’s Teraflop  [10]). In particular, the static power consumption accounts for an increasing percentage of the total NoC power due to continuing scaling of transistor size and supply voltage. A recent study shows that router static power can be nearly 64% of the total router power due to the fact that the average network utilization in real benchmarks is relatively low  [7]. Therefore, it is imperative to explore effective approaches that can dramatically reduce NoC static power.

Power-gating is a very promising approach that can significantly reduce static power consumption. It has been proposed and applied to cores and execution units for some time  [11], but only more recently has it been investigated for NoC routers  [4], [5], [7], [8], [14], [16], [15], [19], [21]. Power-gating cuts off power supply to routers when they are idle, thus being able to eliminate the static power of the entire router. Meanwhile, this approach is also prone to incur a considerable increase in packet latency. Packets that encounter a powered-off router must wait for the router to wake up before proceeding, and may experience similar wakeup latency several times as multiple routers along the path to destination could be powered off.

Considering the large potential of power-gating in saving power but also the substantial impact on performance, a couple of works have been conducted to explore productive ways of applying power-gating to on-chip routers. Yet, significant opportunities still exist and need further exploration, particularly given the large number of factors that may influence power-gating effectiveness such as application behaviors, routing algorithm, topology, traffic pattern, etc. To enable exploration along these promising research lines, a cycle-accurate simulation infrastructure that supports closed-loop, full-system simulation is much needed.

In this work, we first identify the key requirements for NoC power-gating simulation and discuss three important optimizations that can enable correct and efficient handling of pipeline draining and handshaking issues that are specific to NoC router power-gating. We then present a useful simulator tool called, Agate, which is a detailed cycle-accurate NoC power-gating simulator that complements Garnet  [1]. The proposed simulator can be integrated into the Gem5 simulator  [3] to conduct full-system simulation. Agate includes features for monitoring the usage of NoC router components in Garnet, suspending and resuming NoC router pipeline, handling the signaling between NoC routers, and modeling NoC router power state transitions effectively. It implements important optimizations to minimize simulation overheads and accurately capture the power-saving potential of various schemes under evaluation. In addition to these features, Agate is also equipped with extensive instrumentation for reporting various power-gating related statistics. The simulator is very flexible as new power-gating schemes can be easily created under the structure of Agate source code. Moreover, Agate is also able to incorporate output from other power/energy modeling simulators at different levels for more accurate power/energy estimation. As an example, the output from the DSENT simulator  [22] has been incorporated in Agate as a source of power input.

The main contributions of this work are three-fold:

• Key requirements of NoC power-gating simulation regarding accuracy, efficiency, full-system compatibility, extensibility and flexibility are identified;

• Insights on the problems, solutions and optimizations generally applicable to NoC power-gating simulation platforms are provided; and

• A cycle-accurate simulator that facilitates research on NoC router power-gating is proposed.

Given the importance of NoC power-gating techniques and the useful features that Agate offers, we believe Agate will be a valuable simulation tool for the NoC community once made publicly accessible. The rest of the paper is organized as follows. Section  2 provides more background and discusses the requirements of simulating NoC power-gating. Section  3 discusses the problems, potential solutions and optimizations in NoC power-gating simulation, and Section  4 describes in detail the proposed Agate cycle-accurate NoC power-gating simulator tool. Section  5 demonstrates the proposed simulator in simulating and evaluating various power-gating schemes. Finally, related work is summarized in Section  6, and Section  7 concludes the paper.