A fully automated reconfigurable calculation engine dedicated to the real-time simulation of high switching frequency power electronic circuits

Abstract

Real-time simulation allows rapid deployment and thorough testing of prototyped hardware in the automotive and aerospace industries. However, the simulation of power electronic circuits (PECs) in the context of PC-based simulations is challenging for several reasons, and imposes a limit in the 1–5 kHz range to the achievable switching frequencies. As FPGA devices gain computing power, conducting the real-time simulation of PECs on chip becomes an attractive alternative. This paper demonstrates the feasibility of high-performance floating-point calculation engines aimed for the real-time simulation of PECs on high-end and low-cost FPGAs as well. The paper discusses emerging paradigms for reconfigurable floating-point computing that favor optimal performance and offer near double precision arithmetic at a minimal hardware cost. The effectiveness of the approach is demonstrated by considering three different circuit topologies and simulating their high-frequency stimulation (20 kHz) using the same automated calculation engine. The considered circuits are a boost converter, a two-level three-phase bridge, and a two-level-three-phase bridge driven by a boost converter.

Introduction

Before resorting to a real hardware prototype, it is a common industrial practice to test electronic control units against a simulated model of a plant. The controller under test and the simulated plant interact in real-time using a so-called hardware-in-the-loop (HIL) configuration. This approach has several advantages: (i) borderline conditions can be safely simulated; (ii) the controller design may start while the plant itself is under development. Modern digital controllers have very small sampling times (≪10μs) that can hardly be injected into a pure PC-based real-time simulation using standard methods, whereas an FPGA-based simulation approach helps overcoming the limitation. Hence, the use of reconfigurable devices in the practice of HIL simulation is emerging as a dominant trend with reported time-steps in the 100–1000 ns range [23], [25].

A number of challenges remain for the broad adoption of this technology in real-world applications. FPGA-based modeling implies the complete design of an application-specific processor for solving ordinary differential equations. Thus, the computational regularity in problem formulation is a key to the rapid implementation of hardware solvers [20]. The representation of reals is another important concern for on-chip simulation. Two main alternatives are acknowledged in the literature: the fixed-point (FXP) and the floating-point (FP) formats. FPGA devices offer all the basic arithmetic operators needed for FXP arithmetic (adder, multiplier…). Conversely FP operators are more complex, occupy more area and have higher latencies than their FXP counterpart [20]. Hence, while the FP format solves the dynamic range problem and permits the implementation of complex DSP algorithms, it may also bring a speed and area penalty. Finally, considering a system clock period in the 5–10 ns range, the time budged allowed to perform all the computations needed at each time point of the simulation is limited to 10–100 clock cycles. These facts favor the following arguments: (1) a wise pre-calculation of certain computationally-intensive parts of the mathematical model is mandatory to achieve high performance; (2) custom FP operators and non-standard FP formats offer elegant and powerful workarounds to the implementation of very precise and compact solvers on FPGA [1], [2], [15].

The FPGA-based simulation of power electronic circuits is another important challenge. In the automotive and the aerospace industries, the real-time simulation of the power converters necessitates calculation time-steps in the sub-microsecond range because typical switching frequencies of these circuits are in the 10–200 kHz range [6], [29], and the guidelines for accurate modeling of power electronics suggest times-steps that are about 20 times smaller than the period of the switching frequency [5]. This yields time-steps in the 0.25–5 μs range, which are unreachable or hardly achievable in the context of a CPU-based HIL simulation, since the expected time-steps are in the 5–10 μs range at best. The simulation of switching networks traditionally falls into two modes [10]: the detailed-mode and the behavioural-mode. Detailed-mode simulation is found in such commercial softwares as SABER and SPICE, where the switch model is formulated in terms of non-linear functions that are very computationally intensive, and therefore unusable in real-time simulation. Hence, behaviour-mode simulation is consubstantial to HIL simulation.

Three types of switch models are acknowledged as belonging to the behavioural-mode simulation [10]: (1) the ideal model; (2) the switching function model; and (3) the average model. All these models have been used for the real-time simulation of PECs, the ideal switch model and the switching function models being mostly used [3], [4], [18]. Switching function models are very powerful and have been used for the simulation of power converters with open and short faults [4], but their usage is heavily dependent upon the circuit topology and necessitates an elaborate identification of all possible modes of the converter. In the ideal-model on the other hand, the switch is either an ideal switch or a binary resistance (R_on/R_off), and the model has the nice property of handling each switch individually. However, it involves the reformulation of network equations for every combination of the switch statuses. In the early nineties, an effort has been made to develop a switch model that handles each switch individually while keeping the network equations fixed regardless to the switch status [7], [8], [22]. This fixed-admittance model has gained a lot of interest for real-time simulation applications [11], [13], [16] and is used here for modeling PECs as well.

In [21], we presented a solver topology based on custom floating-point multiply-accumulate (MAC) cores suited for on-chip power electronic circuits simulation using the fixed-admittance switch modeling technique. This paper is a continuation of that work and proposes the following elaborations: (1) In order to demonstrate the generic nature of the proposed calculation engine, a fully automated version of the calculation engine is presented in this paper and validated against three different topologies of power electronic circuits; (2) The effectiveness of the previously proposed custom floating-point format (designated as the self-alignment format – SAF) is confirmed in this paper by considering a more thrifty version of it, without compromising precision; (3) The topology based on parallel MACs is replaced by a parallel dot-product (DP) operators approach in order to enhance the computing power of the engine and to help it favorably cope with complex circuits; (4) Network equations are expressed using the modified nodal analysis (MNA) instead of the Tableau approach.

The remainder of this paper is organized as follows: Section 2 proceeds with the presentation of the associated fixed-admittance switch modeling technique. It also shows how the MNA equations must be rewritten for an efficient FPGA execution. Section 3 discusses the design of custom FP operators using the SAF and presents the architecture of the automated calculation engine based on parallel DP operators. Section 4 presents the simulation results for the automated calculation engine, along with a discussion about its speed performance and area occupation. Results are given for a high end FPGA (Virtex 5) as well as a low-cost FPGA (Spartan 3). Section 5 concludes this work and forecasts the future developments to come.