RESURF LDMOSFET with a trench for SOI power integrated circuits

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Abstract

A new structure of RESURF LDMOSFET is proposed, based on silicon-on-insulator, to improve the characteristics of the breakdown voltage and the specific on-resistance, where a trench is applied under the gate in the drift region. A trench is used to reduce the electric field under the gate when the concentration of the drift region is high, thereby increasing the breakdown voltage and reducing the specific on-resistance. Detailed numerical simulations demonstrate the characteristics of this device and indicate an enhancement on the performance of the breakdown voltage and the specific on-resistance in comparison with an optimal conventional device with LOCOS under the gate.

Introduction

Intelligent power integrated circuits (PICs) have become increasingly popular for implementation of system functions with improved performance, reduced size, low cost, and low power consumption. For example, the flat panel display industry has made effective use of PICs to offer improved features. In particular, a plasma display panel requires the power devices with the breakdown voltage above 100 V (in the data driver IC) or 200 V (in scan driver IC) [1], [2], [3]. The lateral double-diffused MOSFET (LDMOSFET) structure is commonly used devices in such circuits. In the case of LDMOSFET, the use of fine lithography cannot reduce the size imposed by the drift region as the breakdown voltage of LDMOSFET is a function of the doping and length of the drift zone [4]. Some structures have been proposed to increase the breakdown voltage by reducing the surface electric field at the end of the gate plate for the devices of which the breakdown voltage is under 100 V on the bulk silicon [5], [6], [7], [8]. Silicon-on-insulator (SOI) has emerged as the technology of choice for fabricating PICs because the buried oxide (Box) provides an effective way of isolating the low-power CMOS from the high-side and low-side power devices, preventing such problems as induced over-voltages and latch-up, without having to resort to using expensive deep wells. This advantage has spawned a great interest in fabricating PICs in SOI [9], [10], [11], [12].

We propose a new type of REduced SURface Field (RESURF) [13] LDMOSFET which is called the Trench LDMOSFET based on SOI in which a trench is applied under the gate in the drift region, and the electric characteristics are investigated using a process simulation program, ATHENA and a 2D device simulation program, ATLAS. With a trench applied in the device the electric field under the gate edge has been alleviated and the doping concentration of the n-drift region can be increased, thereby increasing the breakdown voltage and reducing the specific on-resistance compared with the conventional RESURF LOCOS LDMOSFET. As a result, the trade-off between the between the breakdown voltage and the specific on-resistance (Ron) is improved.

Section snippets

Device structures

Schematic cross-sections of the conventional LOCOS LDMOSFET and the proposed Trench LDMOSFET are shown in Fig. 1. Generally, the breakdown voltage of the conventional SOI LDMOSFET is limited by the buried oxide thickness, SOI thickness, the drift region length and the drift region concentration. To compare the characteristics of the proposed Trench LDMOSFET with the conventional LOCOS LDMOSFET, the basic parameters of the structure, except the drift region dose and the trench depth, were fixed

Simulation results

The main performance parameters for smart power devices are the specific on-resistance (Ron) and the breakdown voltage, which are inversely related to each other. As such, the optimum design between the breakdown voltage and the Ron is the main issue for high voltage LDMOSFET devices. A trench under the gate edge in the drift region can increase the breakdown voltage by reducing the electric field there, while slightly reducing the Ron by increasing the doping concentration of the drift region.

Experimental results

A new device of 350 V SOI LDMOSFET for PDP scan driver IC is designed and implemented. The various processing steps are designed using 2D process simulator ATHENA [11]. The starting SOI substrates have a 8 μm thick silicon layer and a 3 μm thick buried oxide. The background doping concentration of the silicon layer is 1×1015 cm−3. The standard CMOS process was used except the process for a trench. The process begins by ion implantation for the p-well and the n-drift region. The doses for p-well

Conclusion

We propose a new type RESURF LDMOSFET base on SOI to improve the trade off between the breakdown voltage and the specific on-resistance. The proposed structure has a trench under the gate in the drift region, with this structure the electric field at the silicon surface under the gate edge is reduced so the breakdown voltage can be increased and drift dose can be increased so the specific on-resistance can be reduced. From the simulation results, the voltage handling capability and the specific

Acknowledgements

This work was supported by grant No. (R12-2002-055-02001-0) from the Basic Research Program of the Korea Science and Engineering Foundation.

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