Elsevier

Microelectronics Journal

Volume 35, Issue 10, October 2004, Pages 805-810
Microelectronics Journal

Extraction of material parameters based on inverse modeling of three-dimensional interconnect fusing structures

https://doi.org/10.1016/j.mejo.2004.06.011Get rights and content

Abstract

An approach for determining higher order coefficients of the electrical and thermal conductivities for different materials is presented. The method is based on inverse modeling using three-dimensional transient electrothermal finite element simulations for electrothermal investigations of complex layered structures, for instance polycrystalline silicon (polysilicon) fuses or other multi-layered devices. The simulations are performed with a three-dimensional interconnect simulator, which is automatically configured and controlled by an optimization framework. Our method is intended to be applied to optimize devices with different material compositions and geometries as well as for achieving an optimum of speed and reliability.

Introduction

Semiconductor process technology nodes in the submicron regime often use polycrystalline silicon (polysilicon) fuses as one-time programmable devices which provide memories up to several kilobits and offer a cheap, efficient, and area-saving alternative to small non-volatile memories for System-on-a-Chip solutions. Approaches to increase the memory density by using 3-state fuses of layered materials have been reported [1]. Another important application is the use of simple field programmable gate arrays for trimming CMOS circuits to obtain a specific analog performance [2]. Furthermore, the fuses allow to provide variable elements such as trimable resistors or capacitor arrays [3]. Finally, the fuses may act classically as protective elements for improved protection and replacement of critical components before actual failures [4].

Programming is performed by sending a current pulse through the fuse, resulting in opening the polysilicon film after transition to a second-breakdown state. The transition occurs when parts of the polysilicon layer reach the silicon melting point, and the molten silicon is transported from the negative end through drift of ions in the applied field [5]. Fuses implemented in deep sub-micron technologies become more and more attractive in terms of power and area consumption, and hybrid approaches using other materials are losing importance [6]. Nevertheless, going to smaller ground rules below 350 nm implies decreasing the supply voltages to 1.5 V and below [7]. This constraint requires a careful optimization of the fuse layout, ensuring an efficient and reliable programming mechanism [8] and minimizing the necessary power consumption of the fusing process. As the fusing process takes place in a short time interval (between a couple of 10 ns for an applied voltage step up to the range of microseconds for a voltage ramp (c.f. Fig. 3, Fig. 4), direct thermal measurements of this process are hard to obtain. Previously carried out work [9] already shed some light on the physics behind the fusing mechanism, but the optimization of the fuse structure for reliable and fast fusing was only possible via expensive experimental work by using test chips.

Our work focuses on gaining better insight into the material characteristics used in the structure, to enable a layout optimization through simulation. Since the electrical and thermal properties of polysilicon are complex functions of polysilicon film doping, grain size, and grain morphology [10], the average electrical and thermal properties as a function of temperature were obtained by measuring the transient resistivity response of the fuse through Joule self-heating and subsequent inverse modeling of the measured data to fit the observed behavior.

The electro-thermal self-heating simulations were carried out with the Smart-Analysis-Package (SAP) for three-dimensional interconnect simulation [11] in combination with Siesta, a TCAD optimization framework combining different simulators with gradient based and genetic optimizers [12].

This approach enables the optimization of the fuse layout significantly saving costs normally spent in design and production of layout test chips. Furthermore, a better insight into the transient electro-thermal effects occurring in the first couple of microseconds was gained.

Section snippets

Polysilicon fuse measurements

An industry standard deep submicron polycide gate CMOS process is used for the fabrication of the investigated polysilicon fuse devices. On a specialized test chip, multiple different layout variations were placed to find the optimum layout for fast and reliable fusing. A more complicated example of a fuse structure is shown in Fig. 1. The first experiments were performed with rectangular pulses. Nevertheless, due to the steep slope of the fuse terminal voltage the initial fuse heating is not

Mathematical models

For the numerical calculation of Joule self-heating effects two partial differential equations have to be solved. Euler's equationdiv(σ(T)gradφ)=0gives the electric potential φ where σ(T) denotes the temperature dependent electrical conductivity. The power loss density p is obtained by computingp=σ(T)(gradφ)2.The heat conduction equationcpρmTtdiv(λ(T)gradT)=pis solved to obtain the temperature distribution where λ(T) represents the temperature dependent thermal conductivity, cp the specific

Results and discussion

With the simulation framework siesta the thermal coefficients of the conductivities have been computed in order to minimize the difference between the reference data and the simulation results To check the consistency of the setup, all thermal and electrical parameters were used for the automated simulation run, resulting in a total of 10 parameters. The resulting best fit to the measured reference data is given in Table 1. The electrical and thermal conductivities σ0 and λ0 as well as the

Conclusion

We have presented a method to obtain important material parameters by inverse modeling using transient finite element simulations of complex interconnect structures. This method is capable of describing the electrical behavior of interconnect materials over a significant temperature range. Furthermore, it uses the transient thermal self-heating effect to separate different materials and their electrical and thermal properties. Nevertheless, the exact conduction mechanism inside the polysilicon

References (19)

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