Elsevier

Microelectronics Journal

Volume 36, Issue 8, August 2005, Pages 763-769
Microelectronics Journal

An integrated up-converter circuit in 0.8 μm SiGe technology for TV applications

https://doi.org/10.1016/j.mejo.2004.11.011Get rights and content

Abstract

This paper describes an up-converter circuit for a TV tuner chain that can be implemented in both analog and digital TV systems. The circuit is integrated into a low cost standard two metal layer 0.8 μm SiGe technology and is composed with class AB Gilbert cell based active mixer and differential voltage-controlled oscillator (VCO). The use of a high quality balanced inductor in the VCO allows achieving a measured oscillator phase noise of −104.2 dBc/Hz at 100 kHz from the carrier. The frequency conversion is from TV standard IF to RF. The results obtained in a frequency up-conversion from 36 to 1775 MHz are: a conversion gain of −2.25 dB, a noise figure of 14.4 dB and an OIP3 value of 9.1 dBm. The core power consumption is 33 mA from 5 V power supply.

Introduction

In the last few years the advances introduced in the integration technologies for RFICs have made possible the substitution of systems traditionally implemented with discrete components with new systems mostly composed of integrated ones. Among other advantages, this allows a reduction in their cost, weight and size and an increase in their reliability and protection against copies.

One of the systems in which discrete components are being substituted by other integrated ones is the TV tuner [1] highlighted in Fig. 1. This tuner is part of the CATV/MATV satellite receiver system presented in the same figure. The tuner must process an incoming signal of 36 MHz and allocate it into the desired output channel (47–860 MHz band).

A block diagram of this TV tuner is presented in Fig. 2. The first bandpass high selectivity filter is used to eliminate both out of band interferences and adjacent channels. After amplification, the signal is up-converted to 1775 MHz where it is filtered again to eliminate high frequency harmonic components. Finally, the signal is down-converted to one of the output TV channels. As seen in Fig. 2, a mixer and an oscillator make up the presented up-converter circuit. The mixer is active and it is based on the Gilbert cell, whereas the oscillator is differential and it has a cross-coupled configuration with an integrated LC tank.

The aim of this paper is to demonstrate that a frequency up-converter that achieves the restrictive specifications for TV channel processing can be integrated in a low cost standard 0.8 μm SiGe technology.

The global characteristics of the TV tuner determine the two most important specifications of the up-converter:

  • (1)

    A low phase noise for the oscillator, in order to avoid signal emissions on adjacent channels or the inclusion of noise in the selected channel.

  • (2)

    High linearity for the mixer despite its conversion gain and noise figure, in order to avoid intermodulation and modulation distortion.

The phase noise of the oscillator depends mainly on the quality of the passive components of its resonant tank circuit. That is why the way to improve the phase noise of the oscillator is to design passives with good quality factor [2]: a balanced inductor and two PN junction varactors form the tank circuit of the oscillator. The way to improve their quality is described in the next section.

The main characteristic of the Gilbert cell mixer is its high profit, but in this case an improvement in the linearity above the typical value of the Gilbert cell mixer, without too much degradation in conversion gain and noise figure, can be obtained with the use of a class-AB input stage [3].

Although the technology used to implement the integrated circuits is 0.8 μm SiGe, the oscillator has been integrated with only MOS transistors as will be explained later. On the other hand, the mixer has been designed with HBT transistors except for the current source which has been implemented with MOS ones.

Section 2 describes the topology selected for the oscillator and the design of the passive components of the tank, in Section 3 the mixer design is explained and in Section 4 some layout considerations are presented with the up-converter implementation. The measurements of the up-converter circuit are shown in Section 5 and all the results are discussed in Section 6.

Section snippets

Design of the oscillator

The topology and design of the oscillator is presented in this section. As explained below, it has been used a differential cross-coupled configuration with an integrated LC tank. The schematic of the oscillator is shown in Fig. 3.

Mixer design

In order to avoid intermodulation problems due to unwanted signals, the mixer should present a linearity as high as possible without too much degradation in gain and noise figure. The gain of the amplifier that precedes the mixer in the TV tuner is high so the noise figure of the mixer is not a critical parameter. Moreover, in one hand the conversion gain of the mixer must not be high but, in the other hand, it might not have large losses due to the relatively high insertion loss of the RF

Layout considerations

Once the designs of the oscillator and the mixer are completed, the final step to implement the up-converter circuit is the lay out of both of designs. To avoid problems when joining the oscillator and mixer, two series capacitors have been included to isolate the output DC level of the oscillator from the input of the mixer, as seen in Fig. 7. The chip area is 1900×700 μm2.

In addition, some capacitors between the DC voltage pads and ground have been added in order to stabilize the supply

Measurements

The response of the up-converter circuit has been measured on wafer with the E4407B Spectrum Analyzer. For the supply and control voltages Cascade's DCQ-05 PPGPP and ACP40 GSG (Ground-Signal-Ground) microprobes have been used. Supply voltages of the mixer and the oscillator are independent so the power consumption of each component is known. For the input RF and output IF signals the Cascade's ACP40 SGS (Signal-Ground-Signal) microprobes have been employed.

The measurement of the phase noise

Conclusions

Fully integrated core low power consumption VCO, that achieves the specificated phase noise, has been designed. The measured phase noise is −104.2 dBc/Hz at 100 kHz offset from an 1811 MHz carrier. The oscillator has been designed using 0.8 μm MOS transistors. The ability of the CMOS technology to achieve good phase noise results, if a proper LC tank is designed, has been demonstrated. Besides, the use of a varactor ensures obtaining the correct output frequency independently of the process

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