Elsevier

Microelectronics Journal

Volume 37, Issue 9, September 2006, Pages 963-975
Microelectronics Journal

High-temperature and self-heating effects in fully depleted SOI MOSFETs

https://doi.org/10.1016/j.mejo.2006.01.006Get rights and content

Abstract

In this paper, the high-temperature and self-heating effects in the fully depleted enhancement lightly doped SOI n-MOSFETs are investigated over a wide range of temperatures from 300 to 600 °K by using the SILVACO1 TCAD tools. In particular, we have studied their current–voltage characteristics (IDVGS and IDVDS), threshold voltages and propagation delays. Simulation results show that there exists a biasing point where the drain current and the transconductance are temperature independent. Such a point is known as the zero temperature coefficient (ZTC) bias point. The drain current ZTC bias points are identified in both the linear and saturation regions whereas the transconductance ZTC bias point exists only in the saturation region. We have observed that decreasing the film thickness could reduce the threshold voltage sensitivity of the SOI MOSFET with temperature and that the drain current decreases with increasing temperature. We have also noted that due to the self-heating effects, the drain current decreases with increasing drain bias exhibiting a negative conductance and that the self-heating effects reduced at a higher operating temperature. Self-heating effects are more pronounced for higher gate biases and thinner silicon films whereas the bulk device shows negligible self-heating effects.

Introduction

Integrated circuits that are used in military, automobile, nuclear and well-logging industry require high temperature operation (above 150 °C). The excellent physical and electronic properties of silicon make it an important semiconductor material for high-temperature applications. Several technologies have been explored as a possible choice for high-temperature operation. These technologies include CMOS [1], SOI [2], and GaAs [3]. Silicon-based IC is very mature, low cost and accounts for 95% of the world semiconductor market. The use of bulk CMOS device at high temperatures is limited by the presence of latch-up and high leakage current through the well junction. However, the SOI-based CMOS device is a potential silicon-based device to operate at high temperatures. SOI devices have no latch-up and low leakage current due to the absence of the well [4], [5], [6]. The term silicon-on-insulator (SOI) is used to refer to the process where, on top of the oxide insulating layer, a layer of silicon film is used to build active devices and circuits.

Many authors have reported on the advantages of SOI technology for high-temperature applications. Flandre [7] has compared the high temperature characteristics of bulk CMOS devices with SOI-based devices via experiment. Francis et al. [8] has demonstrated the potential of SOI MOSFETs for high-temperature analog and digital applications via device fabrication and measurements. Jeon and Burk [9] have developed a temperature-dependent model for the thin film SOI MOSFETs and Osman [10] has developed a temperature-dependent model for partially depleted SOI (PDSOI) MOSFETs. In designing digital and analog circuits for high-temperature applications, it is desirable to bias the circuits at a point where the current–voltage characteristics show a very little or no variation with temperature. This point is known as the zero-temperature coefficient (ZTC) biasing point. Osman et al. [11] have presented an analytical and experimental investigation of the ZTC bias point of PDSOI MOSFETs in both the linear and saturation regions. They found that the ZTC bias point could be clearly identified up to 300 °C. In this paper, we will study the IDVGS, IDVDS and the gmVGS characteristics and investigate the ZTC biasing point of the fully depleted SOI (FDSOI) MOSFETs using a two-dimensional process and device simulator. The dependences of the ZTC biasing point on the drain bias, SOI film thickness and the gate length will be discussed using TCAD simulations. In addition, we will study the device threshold voltage and the self-heating effects on the output characteristics of an SOI MOSFET at high operating temperatures. The propagation delays in an SOI-based CMOS inverter will also be simulated.

Section snippets

The SOI MOSFET

A cross-section of an SOI MOSFET is shown in Fig. 1. Depending on the film thickness (tsi) and the doping in the silicon film, the SOI MOSFETs fall into two categories: PDSOI MOSFET and FDSOI MOSFET. When the silicon film is thick, only the top portion of the film is depleted and the bottom portion is neutral. There will be no interaction between the front and the back gates. This type of SOI MOSFET is called PDSOI MOSFET. However, when the neutral region is grounded (via independent body

Device simulation

Simulations of the fully depleted enhancement, lightly doped (LDD) SOI n-MOSFET were performed by using the SILVACO TCAD tools. Typical values of the various transistor parameters used in these simulations are shown in Table 1. SILVACO TCAD tool called ATHENA was used to simulate the device structure and ATLAS was used to simulate the current–voltage characteristics [14].

Separation by implanted oxygen (SIMOX) is widely used to make the SOI wafer where the buried oxide layer is formed by

Simulation results and discussion

Simulations of the fully depleted enhancement, LDD SOI n-MOSFET were performed by using the SILVACO TCAD tools. ATHENA was used to simulate the device structure, ATLAS was used to simulate the current–voltage characteristics and SmartSPICE was used to simulate the propagation delays in an SOI CMOS inverter.

Summary and conclusions

Numerical device simulations have been performed in order to investigate the behavior of FDSOI MOSFETs at high temperatures. Based on our results, we can draw the following conclusions:

(a) There exists a bias point where the drain current and transconductance show no temperature variations. Such a bias point is called the zero-temperature-coefficient (ZTC) bias point. The ID-ZTC bias point exists in both the linear and the saturation regions. The VGS at ID-ZTC bias point in the saturation

Acknowledgment

This work is based on research supported by a grant from the Michigan State Research Excellence Fund.

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