Elsevier

Microelectronics Journal

Volume 38, Issue 2, February 2007, Pages 197-202
Microelectronics Journal

Voltage-to-frequency converter with high sensitivity using all-MOS voltage window comparator

https://doi.org/10.1016/j.mejo.2006.11.018Get rights and content

Abstract

A high-sensitivity voltage-to-frequency converter (VFC) using an all-MOS voltage window comparator is presented in this work. The circuit is composed of one voltage-to-current converter, one charge and discharge circuit, and one all-MOS voltage window comparator. The input voltage is converted into a current which in turn triggers the charge and discharge circuit, where a built-in capacitor is driven. The voltage window comparator monitors the variated voltage on the capacitor and generate an oscillated output of which the vibration frequency is linearly dependent to the input voltage. In this way, the worst-case linear range of the output frequency of the proposed VFC is 0–55.40 MHz verified by simulations given a 0–0.9 V input range. The physical measurement of the proposed VFC shows a 0–52.95 MHz output frequency given a 0–0.9 V input range. The error in linearity is better than 8.5% while the power dissipation is merely 0.218 mW.

Introduction

Lots of work have been done to develop the methods for designing sensors which convey information, the values of passive or active elements, into the oscillation parameters, e.g., the magnitude, phase, frequency, or duty cycle of the vibration. The values to be conveyed might be functions of some other factors, e.g., mechanical pressure, magnetic field, or temperature. The variation of the oscillation must faithfully track the corresponding change in these factors. Hence, bandwidth, sensitivity, and linearity are the most important measures to judge the quality of these circuits. Converting the physically estimated values into oscillations is much preferred because the oscillations are more noise immune. Thus, the correctness of the information can be ensured. A traditional VCO (voltage-controlled oscillator) cannot fulfill such a demand, because the linearity and sensitivity of such a conversion are required.

This paper presents a high-bandwidth linear interfacing circuit which converts the sensed voltage into frequency. The frequency output is very much noise resistant compared to other types of outputs, e.g., the magnitude of current or voltage. It meets the requirement for integration with other IP (intellectual property), e.g., uP or communication MAC (media access circuitry). In contrast to the bipolar or BiCMOS implementations [1], [2] the proposed design is realized in TSMC (Taiwan Semiconductor Manufacturing Company) 0.25μm 1P5M CMOS technology. It possesses the advantages of low power, small area and high bandwidth. Although there were several prior CMOS-based converters, they either required an extra OSC [3], or additional timing control signals and many switched capacitors [4], which became overhead in those designs. By contrast, our proposed voltage-to-frequency converter (VFC) is composed of one voltage-to-current converter (V-to-I), and one charge and discharge circuit (CDC) which is driven by the voltage window comparator (VWC). The physical measurement of the proposed VFC on silicon shows a 0–52.95 MHz output frequency given a 0–0.9 V input range.

Section snippets

CMOS voltage-to-frequency converter

The basic theory of voltage-to-frequency conversion is to track the back-and-forth variations of a certain signal level in a pre-determined range. Thus, not only can it be easily carried out by low-cost CMOS technology, but neither external oscillators nor internal PLLs are required in the design.

Implementation of VFC on silicon

The proposed VFC is implemented by using TSMC 0.25μm 1P5M technology. The die photo of the physical VFC on silicon is shown in Fig. 5. The chip size is 440×460μm2, while the core size is 374.5×353.5μm2. The worst-case simulated working range of the input voltage is 0–0.9 V, while the output frequency is 0–55.40 MHz.

Tektronix TDS 680B oscilloscope, HP 8594E Spectrum Analyzer, and HP 1660CP Logic Analyzer are used to measure the performance of the proposed VFC. Figs. 6, 7, and 8, are the measured

Conclusion

This paper has proposed a high-bandwidth VFC. Not only are the sensitivity and output frequency dramatically improved, but the overall manufacturing cost is reduced by not using BiCMOS, and clock control circuitry. On top of these advantages, the proposed VFC consumes only 0.218 mW.

Acknowledgments

This research was partially supported by National Science Council under grant NSC 91-2218-E-110-001 and 91-2622-E-110-004. The authors would like to express their deepest gratefulness to CIC (Chip Implementation Center) of NAPL (National Applied Research Laboratories), Taiwan, for their thoughtful chip fabrication service. The authors also like to thank “Aim for Top University Plan” project of NSYSU and Ministry of Education, Taiwan, for partially supporting the research.

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