Elsevier

Microelectronics Journal

Volume 39, Issue 9, September 2008, Pages 1130-1139
Microelectronics Journal

Design and modelling of a multi-standard fractional PLL in CMOS/SOI technology

https://doi.org/10.1016/j.mejo.2008.01.069Get rights and content

Abstract

This paper deals with the design of a fractional PLL for wireless multi-standard applications. This circuit has been produced using CMOS/SOI technology, with body voltage to control power consumption and phase noise performance. Five standards are covered by this structure: GSM (900 MHz), DCS (1.8 GHz), Bluetooth (2.45 GHz) and 802.11a (5.8 GHz). Based on multi-engine simulators, associated with a hierarchical models library, a virtual RF system platform, which allows designing complex SoCs, is also presented. The PLL, including digital and analogue parts, constitutes a very good benchmark to validate this platform.

Introduction

The advances in deep sub-micronic technologies will encourage the development of a broader variety of autonomous and mobile communicating systems and devices. In the future, the amount of the exchanged informations between devices will continue to increase. That implies the requirement for confident solutions to communicate, store and process personal data and multi-media streams as well. These trusted personal devices (TPDs) must indeed be able to be interfaced with various terminals and networks (GPS, DCS, UMTS, Bluetooth, Wifi, UWB, Wimedia, etc.). The current trend is to make multi-standard transceivers, using multi-frequency synthesizers based on fractional PLL, for example, in which the frequency resolution is infinite. In order to achieve this goal, three ways have been investigated: EDA tools, architecture and technology.

From a technological point of view, CMOS/SOI has some advantages in the production of fractional PLL. Body contact allows control of power in the VCO core by changing the threshold voltage of the transistors [1]. Moreover, due to the high-resistivity substrate, the inductor quality factor is twice as high as in bulk technology. Beyond this major specificity, SOI technology is increasingly used in digital design for high frequencies and low-power applications. Due to the presence of the buried oxide, we could integrate a complex SoC, with digital and radiofrequency functions, without any deterioration of performances, which is the biggest challenge for SOI.

In multi-standard systems, it is necessary to control power in order to optimize consumption according to standard specifications. Deen et al. show the use of body connection for RF blocks in CMOS technology; in this paper we use it in CMOS/SOI [2]. A new PLL architecture is proposed to cover five standards, with only one VCO. By using only one VCO, we can reduce chip area and therefore chip cost. Standard covered by this innovative structure are those most commonly found in telecommunication systems, i.e. GSM, GPS, DCS 1800, Bluetooth and WLAN. The specifications of these different standards are summarized in Table 1. The DCS (as GSM) specifications represent the worst case for the PLL design, which is why we only present in this paper the DCS results.

To decrease the cost price and the time-to-market can be done only by a complete integration of the system. The design of such complex systems requires the development of a single EDA framework composed of multi-engine simulators associated with a hierarchical models library. Up to date, the different blocks of the system are usually specified by different engineers using different EDA tools. Today, system level modelling to optimize transceiver architecture and digital BaseBand (BB) signal processing algorithm use of very fast data flow simulators (Matlab/Simulink, SystemC, C, etc.) for frequency planning, noise budget, Bit Error Rate (BER) and power optimization. But there is a gap between system and RF block design. To cope with the system level specification, we need to mix different levels of abstraction in order to explore the implementation architectures and to validate the final design at the circuit level. Based on the ADVance-MS™ framework [3] associated with a hierarchical analogue and mixed signal-intellectual property (AMS-IP) library, we use this methodology [4] to design the multi-standard fractional PLL.

Section snippets

The virtual RF system platform

The different parts of complex embedded systems are usually specified and designed separately by engineers working with different EDA tools. In the area of TPDs or small communicating objects, it is important to take into account critical design parameters (cost, consumption, channel effects, etc.) at the system design level in order to determine early the critical parts of the design. During the system architecture exploration, one has to be provided a complete hierarchical AMS-IP model

CMOS/SOI technology

The CMOS/SOI technology is now well known and mature, and starts to be popular for low-power low-voltage applications and for complex SoCs, which include analogue and RF parts. In this section, the structure, advantages and drawbacks of SOI technology are pointed out; more details can be found in [9]. The PLL was designed and manufactured using a 130 nm (partially depleted) CMOS/SOI process from STMicroelectronics.

One of the main differences between SOI and bulk technologies is the presence of

PLL architecture

The PLL is based on an innovative VCO architecture covering five standards, with only one VCO, which was developed with a view to designing a one-inductor VCO whose power is controlled by body voltage. Due to the high-quality factor of inductors on SOI technology, we are able to make high-Q LC tank and downgrade it by adding CMOS switches to change the oscillation frequency and keep the same performances as in bulk technology [1]. The VCO is then composed of one resonator, which is fully

Results

The results presented here have been obtained using ADMS 2006.2 and Matlab/Simulink 2006a running of a 2.8 GHz dual-core processor with 8 GByte RAM. The stage of previous modelling allows studying the variations of the performances of PLL according to the characteristics of the different constituting blocks. From these simulation results, we have to size each block and to design PLL so.

Conclusion

This paper demonstrated the feasibility and the efficiency of a virtual RF system platform. We have presented a multi-languages description (Simulink, VHDL-AMS and Spice netlist), multi-engines (Matlab, Eldo and EldoRF), multi-domains (digital: ΔΣ modulator, Dividers; analogue: PFD, CP, filter; and RF: VCO) and hierarchical description levels (system, behavioural, structural and transistor) for simulating a fractional PLL. This platform allowed us designing this PLL, which validated the

Acknowledgements

The authors would like to thank STMicroelectronics for the provision of their 130 CMOS/SOI technology, and the CIM-PACA design platform for its support.

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