Elsevier

Microelectronics Journal

Volume 39, Issue 12, December 2008, Pages 1817-1828
Microelectronics Journal

CMOS realization of two-dimensional mixed analog–digital Hamming distance discriminator circuits for real-time imaging applications

https://doi.org/10.1016/j.mejo.2008.02.004Get rights and content

Abstract

The architecture of an integrated Hamming artificial neural network, and its use as a versatile signal/image processing circuit is presented. The circuit operation relies on the charge-based processing of sum-of-products terms, complemented with digital post-processing. The synthesis of complex functions such as winner-(loser)-take-all, k-winner-(loser)-take-all, rank ordering are demonstrated with a minimal hardware overhead. Different operation modes and corresponding hardware configurations are presented. The VLSI realization of the core two-dimensional Hamming distance discriminator, and the chip measurements are discussed. As such, the presented Hamming discriminator is uniquely suitable for real-time image processing and alignment applications.

Introduction

Over the past decades, artificial neural network (ANN) algorithms have proven to be efficient tools to solve some computationally intensive signal and image processing problems [1]. The complexity of some ANN algorithms has also opened the door to their analog/mixed mode hardware implementation with the main target of accelerating all computations involved [2], [3]. The Hamming ANN is a two-layer feed-forward ANN [4]. The Hamming distance between an input vector and a set of previously stored vectors is computed by the neurons in the first layer, the quantification layer, while the selection of a winner on the criterion of the smallest Hamming distance is performed in the second layer, which is the discrimination layer consisting of a winner-take-all (WTA) unit [5], [6].

Earlier, portions of the Hamming ANN have been successfully integrated on-chip as a pattern classifier using the charge-based mode of operation [7], [8], [9]. The network was implemented using the capacitive threshold logic (CTL) gate described in [10], whereas the WTA circuit was derived as multiple input adaptation of a regular sense amplifier as used in integrated memory circuits. The use of CTL as an analog circuit technique [11], [12], [13] offers several benefits with respect to standard digital CMOS circuit designs, such as low-power of operation, compact design and high-speed processing of weighted sum of very large input vectors qualifying its use in signal processing applications [14], [15], [16]. On the other hand, the analog WTA circuit proposed earlier is very dependent on the technology parameters, i.e. the transistors have to be resized for every new design.

In this paper we show the hardware realization of the Hamming ANN using an extended version of the CTL gate and a digital post-processing to be applied in the time domain. A family of circuits is presented allowing various applications in signal processing, depending on the selected implementation mode. The proposed circuit architecture is described in Section 2, and several operation modes and related possible applications are presented in Section 3. Image processing applications are discussed in Section 4. The fabricated circuit topology and design are described in Section 5, and the experimental results are discussed in Section 6.

Section snippets

Architecture and operation of the Hamming ANN

A modified CTL circuit is proposed in this paper to construct the quantification layer of the Hamming integrated circuit. The quantification layer is connected to analog or digital post-processing depending on the targeted application, to replace regular WTA units. In this case, increased functionality in obtained by operating in the time domain.

The quantification network is made of augmented-CTL gates as depicted in Fig. 1a, where an array of capacitances, CSi are connected between a common

Operation modes, and possible applications

The proposed charge-based circuit can be augmented with different peripheral elements in order to accommodate a number of operation modes. Each arrangement has its own properties and target applications, and is described in this section.

Image processing application and architecture

A two-dimensional array arrangement of the Hamming network where each data input is connected to a horizontal and a vertical row simultaneously, is depicted in Fig. 5a. Closed-loop system evaluation were run using computer simulations. The correction algorithms were intentionally kept very simple in order to maintain a very low hardware overhead. Absolute Hamming distance computation, ramp signal perturbation and regular XNOR Hamming operation were chosen as the working mode.

A simulation

Topology and design

An integrated circuit was realized in a 2P3M 0.35μm CMOS technology, including 32 neurons arranged in a 16×16 array of unit cells Hamming ANN core. The circuit layout of one individual cell is depicted in Fig. 5b. Two CMOS memory bits have been included into each cell in order to increase the versatility of the circuit. Each of these memory points can be replaced by the application specific connection to the desired sensor input; as such the Hamming core can be modified to accommodate on-chip

Experimental results

The circuit performance was measured using a precision ramp generator and a high-speed oscilloscope. Detailed experimental characterization of the circuit has been performed under improved conditions compared to the earlier results presented in [18], and a number of additional tests have been conducted. Fig. 7 shows the ramp perturbation test applied to 16 neurons. Each neuron has a different Hamming distance to the stored pattern, ranging from zero to 15. Full operability in this mode is

Conclusion

The charge-based mixed analog–digital Hamming ANN implementation presented in this work offers a very compact, low-power, and scalable approach for the realization of dense two-dimensional discriminator arrays. A number of operation modes are demonstrated, which proves the versatility of the proposed scheme for a wide variety of applications. The 16×16 Hamming circuit has been realized using 0.35μm CMOS technology, to demonstrate the operational proof of principle. The Hamming ANN discriminator

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