Elsevier

Microelectronics Journal

Volume 40, Issues 4–5, April–May 2009, Pages 656-664
Microelectronics Journal

Towards a framework for designing applications onto hybrid nano/CMOS fabrics

https://doi.org/10.1016/j.mejo.2008.07.072Get rights and content

Abstract

The design of CAD tools for nanofabrics involves new challenges not encountered with conventional design flow used for CMOS technology. In this paper, we propose to define a new framework able to help the designer to map an application on a wide range of emerging nanofabrics. Our proposal is based on a variety of models that capture as well as isolate the differences between these fabrics. This tool supports the design flow starting from behavioral description up to final layout. It integrates fault-tolerant techniques and fabric-related density transformations with more conventional design automation techniques. After an overview of common requirements, physical models, and associated techniques, a case study in the context of NASIC fabrics is used to illustrate some of the concepts.

Introduction

As an alternative to CMOS based designs, novel nanofabrics are being proposed based on a combination of lithographic processes and bottom-up self-assembly based manufacturing. These fabrics include NanoPLA [1], [2], CMOL [3], FPNI [4], and NASIC [5]—to name a few. They are based on a variety of devices such as FETs, spin-based devices, diodes, and molecular switches. Furthermore, all these architectures include some support in CMOS: some like FPNI would move the entire logic into CMOS, others, like NASIC, would only provide the control circuitry in CMOS. The rationale for this varies but includes targeted application areas as well as manufacturability issues.

Other differences include fault handling: e.g., some proposals would use reconfigurable approaches, while others like NASICs would rely on built-in techniques based on redundancy, voting, error correction, and/or unique fabric structures. The architectures proposed range from general purpose processors to programmable logic arrays similar to FPGAs, and to more specialized devices such as cellular arrays and cellular neural networks.

In order to implement an application on a nanofabric, specific tools are already proposed by the respective research groups [1], [5], [6] as CAD tools are necessary to be able to design and evaluate the capabilities of larger-scale systems. As the underlying technologies are still evolving according to advances in devices, manufacturing, and fabric structures, CAD tools for nanofabrics should be made, ideally generic enough to integrate added features or to enable new paradigms as well as comparison between various approaches.

This paper proposes a prototyping CAD tool that considers an explicit specification of the underlying nanofabric. It extends the classical design flow—shown in the Fig. 1—for designing an application from behavioral specifications (e.g., in VHDL, Verilog, or SystemC) onto physical designs. It is based on a range of transformations applied at different levels of description/abstraction of the application/problem that is mapped.

The new design flow proposed incorporates a variety of models associated with the nanofabric to allow optimizations to occur on generic data structures. Through a computational model, an architectural model, a technological model, and a fault model key aspects of a particular fabric can be captured and abstracted. The proposed models interact with the behavioral and the physical tools to produce an abstract layout for the design—starting from a high-level description. Parts that are mapped to nanoscale are separated from parts that use conventional CMOS technology.

Nanoscale fabrics under consideration have the following features:

  • The use of self-assembly based manufacturing techniques, e.g., nanopatterning, fluidic alignment, DNA-based self-assembly, and di-block co-polymers, in conjunction with conventional lithography: this is driving their structure to be quasi-regular such as based on 2-D crossbars.

  • Nanoscale fabrics could be hybrid nano/CMOS structures as opposed to just nanoscale.

  • Nanoscale fabrics are expected to have high defect rates, e.g., in the range of 10+%; thus, defect tolerance techniques need to be incorporated and taken into account in the design of any new CAD tool. In comparison, conventional CMOS designs in 90 nm technology have only 0.4 defects per cm2.

The need to build a new framework able to support large applications based on emerging fabrics is apparent. While not all of the physical constraints are finalized, investigations have began and significant progress is made on all areas. We can expect that the development of a nano CAD framework can reduce the design gap between nanoscale designs and CMOS counterparts. As known, the classical tools are able to map millions of transistors large designs into CMOS technology.

In summary, this paper makes the following key contributions: (1) we propose to develop a new framework able to manage hybrid CMOS/nano architectures based on model specifications; and (2) the classic design-flow is extended to interact with these new models based on new and adapted tools/algorithms. Our broader objective is to develop a framework that could be used by research groups in this field and that could help them in their investigation of new materials, devices, and architectures evaluating implications at the system level.

The paper is organized as follows. Section 2 presents the proposed models used by this CAD framework to capture the characteristics of the nanofabrics. Section 3 gives an overview of the general organization of the proposed CAD framework. The subsequent sections discuss the main components of the new design flow. The last section shows the feasibility of the approach by taking an example application dedicated to NASIC nanofabric.

Section snippets

Models for fabric specification

The prototyping tool presented here is henceforth referred to as NanoMadeo. It is based on four meta-models. These meta-models provide abstractions of the nanofabrics concerning their computation paradigm (computational meta-model), their structural organization (structural meta-model), technological constraints (technological meta-model), and their fault-tolerance ability (fault meta-model).

Through these, the designer is able to capture different aspects of the target fabric. These models

Design flow

The general flow of the framework for nanofabrics enlarges the classical flow introduced in Fig. 1 by adding an explicit specification of the fabric. The fabric specification is expressed through four models based on the meta-models presented in the previous section. These models interact with the transformations applied at one specific level of description (behavioral, structural, or physical) and interact with processes that are applied between different levels of description. The modified

Application specification and behavioral transformations

The behavioral description of an application is written in an object-oriented language (ST80) that is similar to the traditional description used in Madeo [8]. The compilation procedure produces directed acyclic graphs (DAGs), which are the intermediate representation (IR) used by NanoMadeo.

Some classical behavioral transformations can be applied on this (IR) in order to perform optimizations, e.g., dead code removal, constant propagation, and node fusion.

Some specific transformations related

Synthesis

The resulting logic is then synthesized in the appropriate type of logic (PLA, LUT, and multi-level logic) as defined by the architectural model. Standard external tools such as SIS [9] can be used for this process. This is done on block-wise basis; each high-level code operation is compiled hierarchically into a single block.

Different levels of operator decomposition can be applied, allowing the complexity of each block to be traded off against the number of blocks. The synthesis process may

Physical design

Nanofabrics are generally organized into tiles, hypertiles or nanoblocks that correspond to clusters of PLAs, basic cells, or hypercells. The partitioning techniques used to define such blocks are based on clustering heuristics for PLA packing, as in PLAmap [12], T-VPACK [13], or the Singh algorithm [14] (Table 1).

The parameters for clustering are the number of elementary cells or P-terms of the PLA and the number of inputs and outputs associated with the cluster. The placement problem consists

Illustration of the framework: NASIC case study

Table 1 presents some particularities of four emerging nanoscale fabrics and which model can capture them best. For additional clarification of the NanoMadeo framework, the rest of this section is structured as a case study on NASIC fabric architecture.

Conclusion

In order to handle next generation hybrid nano architectures, CAD tools will have to evolve. Highly heterogeneous multi-part fabrics introduce new challenges which must be met efficiently. In this paper, we have shown that the proposed tool, NanoMadeo, can handle many of these challenges and can be used productively for work on NASIC designs. Its design will make it easy to adapt it for other hybrid nanoscale architectures.

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