Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO

doi:10.1016/j.mejo.2008.08.017

Microelectronics Journal

Volume 40, Issue 1, January 2009, Pages 95-103

https://doi.org/10.1016/j.mejo.2008.08.017 Get rights and content

Abstract

Design optimization for performance enhancement in analog and mixed-signal circuits is an active area of research as technology scaling is moving towards the nanometer scale. This paper presents an approach towards the efficient simulation and characterization of mixed-signal circuits, using a 45 nm CMOS voltage controlled oscillator (VCO) with frequency divider as a case study. The performance characteristics of the analog and digital blocks in the circuit are simulated and the accuracy issues arising due to separate analog and digital simulation engines are considered. The tremendous impact of gate tunneling current on device performance is quantitatively analyzed with the help of an “effective tunneling capacitance”, which allows accurate modeling and simulation of digital blocks with almost analog accuracy. To meet the design specifications of the analog VCO using digital CMOS technology, we follow a design of experiments (DOE) approach. The functional specifications of the VCO optimized in this design are the center frequency and minimization of overall power consumption as well as minimization of power due to gate-oxide tunneling current leakage, a component that was not important in previous generations of CMOS technologies but is dominant at 45 nm and below. Due to the large number of available design parameter (gate-oxide thickness and transistor sizes), the concurrent achievement of all optimization goals is difficult. A DOE approach is shown to be very effective and a viable alternative to standard design exploration in the nanometer regime.

Section snippets

Introduction and motivation

Analog and mixed-signal simulation is becoming an important component of the design cycle that affects both time-to-market and product cost of many modern electronic systems, particularly for system-on-chip (SoC) designs [1]. The operation of analog circuits is very sensitive on mismatches between the components and their dynamic range is limited by noise, offset and distortions. The situation will be further complicated when design will be performed using nanoscale CMOS transistors that are

Contributions of this paper

The contributions of this paper are multi-fold, but can be grouped under two different aspects: use of DOE for designing nano-CMOS VCOs and accounting for the gate-oxide leakage effect in mixed-signal design and simulation. To the best of our knowledge, this is the first time that DOE is used for the simultaneous optimization of center frequency and power consumption with emphasis on gate tunneling leakage power.

First we designed a VCO with frequency divider using a 45 nm CMOS process. We

Related research

Several VCO and PLL designs have been presented in the literature [10]. High performance CMOS based VCO designs have been achieved using analog feedback control [11]. Low-power PLL designs can be achieved by reducing $V_{dd}$ which is a trend identified early in analog CMOS system design [12], [13]. In [14], a comparative analysis between NMOS and PMOS VCOs has been performed and it was concluded that NMOS based VCOs are beneficial in terms of high frequency and low voltage. Concepts related to

Analog vs. mixed-signal simulation: a comparative perspective

The main goal of today's large digital CMOS SoCs with analog components built on the same substrate is low power and high frequency of operation. The performance of SoCs is driven by the digital portion of the SoC which follows market dynamics. This can be achieved to a large extent by implementing mixed-signal circuits, if the integration of both the analog and digital circuits is made efficient in terms of high frequency, low power, and small area. At the same time, analog figures of merit

Phenomenon of tunneling through gate oxide of a nano-CMOS device

The continuous shrinkage of CMOS device dimensions has resulted in a corresponding scaling of gate-oxide thickness as well. The scaled oxide gives rise to the phenomenon of gate-oxide tunneling leakage. A brief overview of the physical phenomenon associated with tunneling leakage is presented in this section.

With the decrease in the thickness of the gate oxide, there is a corresponding increase in the electric field across the gate. The increase in electric field along with the decreasing

Design of a nano-CMOS VCO

The design type of VCO selected for this work is of the “current starved” type [39]. This is essentially a ring oscillator, comprised of an odd number of inverters each biased by a complementary pair of transistors operating as current sources, as shown in Fig. 2. The function of the current sources is to limit the amount of current supplied to the inverter (starve the inverter). An additional pair of transistors acts as an input stage with very large input impedance.

The operating frequency of

Optimization of VCO via DOE

Once a baseline design has been accomplished, we proceeded to optimize its performance. Three basic performance criteria were identified: (1) the frequency response with respect to input voltage (measured by center frequency, achieved when the input voltage is equal to the supply), (2) the total power consumed by the VCO, and (3) the power consumption due to gate-oxide tunneling current.

The fundamental parameters under design control are the sizing of the various transistors ( $W / L$ ratio) and the

Mixed-signal simulation of the VCO with frequency divider

Usage of nanometer CMOS VCO circuits is necessarily increasing due to their wide usage in many RF based communication systems. For different range of frequencies, different topologies can be used. In a PLL, the frequency from the VCO is changed either by changing the reference signal or the divide by ratio of the frequency divider. Due to the stability of the reference signal, a frequency divider is used which divides the frequency from the VCO, so that the frequency matches with the reference

Accuracy in mixed-signal simulations: impact of gate leakage and proposed remedy

Following the different simulation modes as presented in Section 8 the following operating frequencies were obtained: $f_{VCO} = 717.96 MHz,$ $f_{a} = 357.9 MHz,$ $f_{d} = 394.03 MHz .$ In these expression, $f_{VCO}$ is the frequency at the output of the VCO, $f_{a}$ is the frequency at the output of the analog frequency divider and $f_{d}$ is the frequency at the output of the digital frequency divider.

It can be seen that there is a significant difference in the simulation results, depending on whether the frequency divider is

Summary and conclusions

As a result of technology scaling, there is a degradation in the performance of purely analog circuits due to gate tunneling, as discussed in this paper. An analysis of mixed-signal simulations over pure analog simulations for a 45 nm voltage controlled oscillator (VCO) and frequency divider was performed which clearly highlights issues in mixed-signal simulations due to the additional leakage mechanism. An approach to equalize the frequency at the outputs of analog and digital blocks is given

Acknowledgments

The authors would like to thank the editors and reviewers for their critical comments which enhanced significantly the quality of this paper. The authors would also like to thank Gayathri Sarivisetti, graduate of the University of North Texas. This work is supported in part by NSF award number 0702361.

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^☆: Preliminary versions of this research have been presented in the following conferences: G. Sarivisetti, E. Kougianos, S.P. Mohanty, A. Palakodety, and A.K. Ale, “Optimization of a 45 nm CMOS Voltage Controlled Oscillator using Design of Experiments”, in Proceedings of the IEEE Region 5 Technology and Science Conference, pp. 87–90, 2006. S.P. Mohanty and E. Kougianos, “Impact of Gate Leakage on Mixed Signal Design and Simulation of Nano-CMOS Circuits”, in Proceedings of the 13th NASA Symposium on VLSI Design, 2007.

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Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO☆

Abstract

Section snippets

Introduction and motivation

Contributions of this paper

Related research

Analog vs. mixed-signal simulation: a comparative perspective

Phenomenon of tunneling through gate oxide of a nano-CMOS device

Design of a nano-CMOS VCO

Optimization of VCO via DOE

Mixed-signal simulation of the VCO with frequency divider

Accuracy in mixed-signal simulations: impact of gate leakage and proposed remedy

Summary and conclusions

Acknowledgments

Analog and digital design in 65 nm CMOS: end of road?

Analog circuits in ultra-deep-submicron CMOS

IEEE J. Solid-State Circuits

A dual dielectric approach for performance aware gate tunneling reduction in combinational circuits

Dual-K versus dual-T technique for gate leakage reduction: a comparative perspective

Phase-Locked Loops, Theory, Design and Applications

A methodology and design for effective testing of voltage-controlled oscillators (VCOs)

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Proc. IEEE

Design and Analysis of Experiments

Monolithic Phase-Locked-Loops and Clock Recovery Circuits

An extended frequency range CMOS voltage controlled oscillator

The design of high-performance analog circuits on digital CMOS chips

IEEE J. Solid-State Circuits

A 2-1600-MHz CMOS clock recovery PLL with low Vdd capability

IEEE J. Solid-State Circuits

A comparative study of MOS VCOs for low voltage high performance operation

Jitter in ring oscillators

IEEE J. Solid-State Circuits

Analog circuit performance issues with aggressively scaled gate oxide CMOS technologies

Design of a ring-oscillator with a wide tuning range in 0.13 μm CMOS for the use in Global Navigation Satellite Systems

Jitter in ring oscillators

IEEE J. Solid-State Circuits

Jitter and phase noise in ring oscillators

IEEE J. Solid-State Circuits

20 GHz integrated CMOS frequency sources with a quadrature VCO using transformers

Power optimized LC VCO and mixer co-design

A 1.8 V fully integrated dual-band VCO for zero-IF WiMAX/WLAN receiver in 0.18μm CMOS

Dual- $K$ versus dual- $T$ technique for gate leakage reduction: a comparative perspective

A 2-1600-MHz CMOS clock recovery PLL with low $V_{dd}$ capability

Design of a ring-oscillator with a wide tuning range in 0.13 $μ$ m CMOS for the use in Global Navigation Satellite Systems

Power optimized $LC$ VCO and mixer co-design

A 1.8 V fully integrated dual-band VCO for zero-IF WiMAX/WLAN receiver in $0.18 μ m$ CMOS