Design and simulation of sequential circuits in quantum-dot cellular automata: Falling edge-triggered flip-flop and counter study
Introduction
As conventional CMOS technology hits its fundamental feature size limit, recent years have seen a number of research efforts that have focused on new devices that might replace CMOS technology [1]. One of the promising emerging devices is Quantum-dot Cellular Automata (QCA) [2], [3], [4], [5]. Originally proposed by Lent et al. [2], QCA uses arrays of coupled quantum dots to build Boolean logic functions [6] and to perform useful computations. So QCA not only offers a solution to bottleneck of scaling feature size, but also a new way of information transformation. Moreover, conventional digital technologies use ranges of voltage or current to represent binary values. In contrast, QCA uses the position of electrons in quantum dots to represent binary values 0 and 1. Consequently, the primary advantages of QCA are the exceptionally high logic integration derived from the small size of dots, and with the notably low power consumption.
QCA can be used to implement combinational circuits by properly arranging cells in series. So far, several studies have been reported about combinational circuit design, such as QCA Full Adder [7], [8], Multiplexer [9] and Programmable Logic Array [10], etc. At the same time, memory circuits have also attracted some attentions, such as QCA random access memory [11] and serial memory [12], etc. Actually, flip-flops are also very important quantum-dot cellular automata (QCA) circuits because they are expected to be used for designing and realizing large scale sequential circuits, for example counter. Anteriority, some works about sequential circuits design have been published, like QCA R-S flip-flop [9], [13], [14], D flip-flop [13], [14], [15] and Semaphore sequential circuit [13]. But to our knowledge, QCA flip-flop and sequential circuit designs have not been widely studied. The objective of this paper is to propose two detailed falling edge-triggered design by utilizing special QCA clock zones with an input Clock Pulse (CP) to realize J-K flip-flop (J-K FF). Ulteriorly, counter designs have not been considered by QCA designers. As an application to falling edge-triggered J-K flip-flop, QCA n-bit synchronous counters and their characters are examined. QCA sequential design schemes are inherently pipelined and require device and clocking methodology that differs significantly from conventional CMOS designs. Due to the importance of the QCA clock in creating actual designs, it will be discussed in detail in Section 2.
This paper is organized as follows: In Section 2, a brief background of QCA technology and its clock phase scheme and clock zone signal are presented. In Section 3, the design and implementation of falling edge-triggered and J-K flip-flop are shown. In Section 4, as an application of the proposed J-K flip-flop to sequential circuits, n-bit QCA synchronous counters are presented. In Section 5, simulation results and different bit size counters characters are shown. Conclusions are given in the last Section.
Section snippets
QCA review
The basic building block of QCA devices named cell is presented in Fig. 1(a). QCA cell consists of four quantum dots in a square array coupled by tunnel barriers, two electrons are injected into the cell. Due to Coulombic repulsion, the two electrons reside in opposite corners representing two polarizations [16].
QCA Edge-triggered J-K flip-flop design
In this section, falling edge-triggered mechanisms and its QCA implementation are discussed. Then J-K flip-flop is designed with falling edge-triggered structure. In all the design of this paper, QCA cells have a width and height of 18 and 5-nm-diameter quantum dots. They are placed on a grid with a cell center-to-center distance of 20 nm. For circuit layout and functionality checking, all designs were simulated using bistable approximation simulation method in QCADesigner [18]. QCADesigner is a
Synchronous counter implementation
Using J-K flip-flop and additional combinational logic circuits, any sequential logic circuits can be designed. The most important sequential circuits that are widely used in digital systems are counters and registers, i.e. counters can be used to count pulse, time and divide frequency. This paper only presents mod 4 and mod 8 counters. Fig. 8 shows the layout of mod 4(2-bit counter) applying falling edge-triggered J-K flip-flop. In this design, two J-K flip-flops are applied; both are clocked
Function simulation of J-K flip-flop
To illustrate and check the function of proposed falling edge-triggered J-K flip-flop clearly, QCADesigner is used to simulate the circuit presented in Fig. 7. The input and output waveform of J-K flip-flop is shown in Fig. 10, with test input vectors J=1111001111; K=0011001111 and CP=1010101010. From the output Q we find J-K flip-flop operates at the falling edge of the CP and its function corresponds to the above analysis in subsection 3.2. We label the state transfer and corresponding
Conclusion
Flip-flop is an important part of sequential circuits. This paper has proposed falling edge-triggered methods of flip-flop and presents detailed analysis of designed circuits in QCA. These include J-K flip-flop as well as counter circuits. Initially, two QCA falling edge-triggered structures and J-K flip-flop insensitive to environment noise have been presented, which require an ingenious clock zones arrangement; secondly, an application to J-K flip-flop is studied extensively. QCA synchronous
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2019, OptikCitation Excerpt :The proposed designs include a small number of cells considering simulation results. Finally, Yang et al. [29] have utilized the unique QCA characteristics and clock zones to design falling edge-triggered J-K-flip-flop. They also have explored the design of synchronous counters with several different bit sizes.