Design and simulation of octal-to-binary encoder using capacitive single-electron transistors (C-SETs)

doi:10.1016/j.mejo.2010.08.021

Microelectronics Journal

Volume 42, Issue 1, January 2011, Pages 96-100

https://doi.org/10.1016/j.mejo.2010.08.021 Get rights and content

Abstract

This paper presents an octal-to-binary encoder that is designed using capacitive single-electron transistors (C-SETs). The design parameters are calculated by considering each C-SET as a switching device in pull-up configuration. Logic circuit is based on voltage state logic. The designed circuit was simulated using SIMON 2.0, which is based on Monte Carlo and master equation (MC–ME) methods. The simulation results verify the operation of octal-to-binary encoder.

Introduction

Tunneling phenomena and Coulomb blockade are two basic principles of single-electron devices (SEDs), which reveal the quantized nature of electron charge [1]. Low power dissipation, miniaturized device size and scope for further miniaturization make SEDs a potential candidate for implementation of logic circuits. To use these features in ultra-large scale integrated circuits (ULSI), hybrid circuits consisting of SET for logic and CMOS for amplification have been proposed [2], [3]. SEDs are used either in charge state logic (representation of one bit by presence/absence of single electron on the dot) or in voltage state logic (representation of bit by more than one electron and using SEDs to switch current ON/OFF) [4], [5]. It is evident that charge state logic consumes very less power in comparison to voltage state logic, but in case of charge state logic, even one erroneous electron can give the wrong conclusion. From circuit stability point of view, voltage state logic is considered better [2]. SEDs have many applications in digital logic gates, analog-to-digital converters, supersensitive thermometer, memory elements, etc. [6], [7], [8], [9]. There are several simulators for design and simulation of single-electron devices and circuits [6], [10], [11], [12]. A popular simulator is SIMON, which was developed by Wasshuber and Kosina [13] for design and simulation of single-electron devices and circuits. Various types of logic gates and digital circuits, e.g. inverter, XOR, half adder and decoder, have been implemented using SEDs [14], [15], [16], [17], [18].

This paper presents the design of C-SET based octal-to-binary encoder that was simulated using SIMON 2.0 [13]. Though the Monte Carlo approach provides better transient and dynamic characteristics with the ability to trade-off accuracy with simulation time, it creates numerical instability and takes very long simulation time to simulate rarely occurring events, e.g. cotunneling event in SEDs. In SIMON, this problem is overcome by combining the Monte Carlo with master equation method (MC–ME). The combined approach first divides all events into frequently and rarely occurring events, and then solves the events using Monte Carlo and master equation method, respectively. The designed octal-to-binary encoder is made of multiple identical C-SET transistors. To make the designed circuit stable, individual single C-SET must work in the stable region. Therefore to ensure the stability of single C-SET, ON/OFF voltage values are calculated analytically. The simulated results for every octal input are presented here, which verify the truth table and operation stability of the designed encoder.

Section snippets

Single-electron transitor as a logic element

Single-electron circuits consist of tunnel junctions, capacitors, quantum dots and power supplies. There are two basic essential conditions for single electronics. First, the energy required to charge the quantum dot by one electron should be larger than thermal energy: $E_{c} ⪢ k T$ $E_{c} = e^{2} / 2 C_{dot}$ where k is the Boltzmann constant, C_dot the capacitance of quantum dot and e the electron charge.

Second, to assure localization of electron on the quantum dot, tunnel resistance (R_t) must be higher than quantum

Design of single-electron octal-to-binary encoder

A 2ⁿ-to-n binary encoder has 2ⁿ input and n output lines. When one of 2ⁿ inputs is 1, the output corresponding to active input will be in the form of n-bit binary number. The truth table of octal-to-binary encoder is shown in Table 1.

For an octal-to-binary encoder, the logic expressions can easily be derived from the above truth table. $Y 0 = V 1 + V 3 + V 5 + V 7$ $Y 1 = V 2 + V 3 + V 6 + V 7$ $Y 2 = V 4 + V 5 + V 6 + V 7$

The output logic expressions are independent of V0, which means for active V0, all binary output bits are ‘0’. Therefore

Results and disscussion

The graph of input voltages V1–V7 vs. time variation is shown in Fig. 3. The calculated voltage values 0.112 and 0 V are choosen for high and low logic input bits, respectively. The outputs Y2, Y1 and Y0 are the voltages of the nodes at which the C-SET and the load capacitor are connected. The other ends of all three load capactiors are connnected to the ground.

The measured output voltage values are shown in Fig. 4. The outputs of 21.82 mV for high logic and 11.64 mV for low logic are obtained.

Conclusions

Voltage state logic based octal-to-binary encoder has been designed using C-SET and the circuit was simulated using SIMON 2.0. The required gate voltage for switching transistor ON was calculated. The designed circuit has 12 identical C-SETs and three load capacitors, across which output voltages are measured in the form of binary bits Y2, Y1 and Y0. The truth table was verified for octal input. The free energy diagrams and stability plots provide confirmation of stability of the designed

Acknowledgements

The authors express sincere thanks to Dr. Chandra Shekhar, Director CEERI, Pilani, for encouragement and his keen interest in design and simulation of single-electron devices. The reported work has been carried out under a sponsored project from the Department of Information Technology (DIT), Ministry of Communication and Information Technology, New Delhi, Government of India. Their financial support is gratefully acknowledged.

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Design and simulation of octal-to-binary encoder using capacitive single-electron transistors (C-SETs)

Abstract

Introduction

Section snippets

Single-electron transitor as a logic element

Design of single-electron octal-to-binary encoder

Results and disscussion

Conclusions

Acknowledgements

Microelectronics Journal

Superlattices and Microstructures

Microelectronics Journal

Microelectronics Journal

Microelectronics Journal

Single-electron devices and their applications

Proceedings of the IEEE

A new design scheme for logic circuits with single electron transistors

Japanese Journal of Applied Physics

Single-electron logic cells and SET/FET hybrid integrated circuits

Journal of Semiconductor Technology and Science

Complementary digital logic based on the “Coulomb blockade”

Journal of Applied Physics