A high-speed current conveyor based current comparator

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Abstract

In this paper, a new high-speed current mode comparator based on inherent current conveyor and positive feedback properties is presented. This novel approach has resulted in major reduction of the response time and hence a wide band application of the circuit. Simulation results using HSPICE and 0.18 μm CMOS technology with 1.8 V supply confirms a propagation delay of less than 0.4 ns in the high frequency range of 700 MHz with 158 μw power dissipation. Under the above conditions, the accuracy of the input current is as low as 50 nA.

Introduction

Current mode circuits have used quite regularly due to their wide dynamic range, low voltage operation, wide bandwidth and low power dissipation properties [1]. Comparator is an important part of many analog integrated circuits. Current comparators are used broadly in high data conversion especially in analog to digital converter (ADC). Traff [2] proposed the first current mode comparator. The design is based on the combination of two inverters with positive feedback. Compared with voltage mode comparators the most important drawback of this comparator is the response time of the circuit which restricts the input frequency range. Since then, many new design ideas have been developed in order to improve the above shortcoming as well as other properties such as power consumption, offset consideration and wider input dynamic range [3].

Palmisano and Palumbo [4] have utilized an offset compensation circuit in order to reduce the offset current due to process mismatch. The application of compensation capacitors that are employed in the circuit deteriorate the switching time of the comparator. Cembrano et al. [5] used a nonlinear negative feedback method to achieve high-speed for low current and high accuracy. Others have exploited different circuit ideas such as resistive feedback network [6], negative feedback structure and emphasis on a larger loop-gain [7]. Banks and Toumazou [8] reported a power efficient comparator where, advanced positive feedback network is used to improve the circuit characteristics. A lack of comparable time response with respect to the voltage mode comparators is observed in all the previous treatment of the current mode comparator circuits.

It appears that low input impedance, short propagation delay, power dissipation, and precision are the most critical design parameters for comparators. Based on the above argument, an available approach to improve these criterias is the application of second-generation current conveyor (CCII) circuits [9]. This circuit is employed as basic building blocks in many current mode circuits. Since their introduction in 1968, the interest generated by CCII has increased steadily and is recognized as important versatile analog building blocks. A non-ideal second generation current conveyor (CCII) block diagram is schematically represented in Fig. 1. By applying a voltage to Y terminal, an identical voltage will appear in node X with no current flow into the Y terminal. The voltage in the X node will results in a current flow to the X node as well as an equal current in node Z.

The matrix representation of the above circuit is shown in Fig. 2. In this figure the plus sign of β means that the current is flowing in the same direction in nodes X and Z as shown in Fig. 1 and when in opposite direction the sign is negative.

The CCII circuit has some important characteristics such as low input impedance for input current in the node X, high output impedance in the node Z, and low power low voltage design capability. These are very useful options for improving the current mode comparators performance.

In this work, the design procedure of a new current comparator using a CCII block as input stage is described in Section 2. Simulation results and comparisons are presented in Section 3.

Section snippets

Circuit design

The current comparator concept as expressed by [3] and shown in Fig. 3 is as follows. The input current (Iin) is injected into the input stage and is converted to the voltage VIN and V1 by amplifier A1. Voltage buffer A2 is acting as transimpedance stage. V1 is amplified using the high gain amplifier (A3) to generate the output logic voltage level.

As shown in Fig. 4, CCII is used as the input stage of the proposed new current comparator due to the low input impedance at node X and the inherent

Simulation results

HSPICE simulations of the proposed switch current comparator are presented using 0.18 μm CMOS technology parameters and 1.8 volte supply. The input current characteristics are shown in Fig. 6. Where, the input current varies between×500 nA. The output voltage of proposed comparator in comparison to previous works is illustrated in Fig. 7. In this figure, the Traff circuit is simulated with 0.18 μm technology. (Table 2).

A response time of such a small magnitude makes it possible to operate this

Conclusion

For the first time, the application of current conveyors to the current comparator circuit is exploited. The simulation results confirm a major enhancement in propagation delay (0.4 ns) and hence the input frequency range (<800 MHz). The power consumption and supply voltage of this newly designed current mode comparator is also reduced quite considerably in comparison with previous reported circuits. Another property of this new generation of current mode comparator is the high precision of the

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