Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist

Abstract

A synthesis tool consisting of coefficient synthesis of architecture, circuit specifications synthesis, and CMOS operational-amplifier (op-amp) synthesis for discrete-time sigma-delta modulators (SDMs) is presented. In circuit specifications synthesis, several major circuit non-idealities are discussed and modeled. A precise performance prediction with a new design flow of specification synthesis is proposed. A hybrid design methodology composed of equation-based and simulation-based approaches for synthesizing fully differential two-stage and folded-cascode op-amps in $0.35\mathrm{\mu }\mathrm{m}$ technology is also presented. Experimental results show that the peak signal-to-noise and distortion ratio (PSNDR) of the fourth-order feed-forward (FF) SDM with an oversampling ratio (OSR) of 64 and a bandwidth of 20 KHz estimated by the proposed synthesis tool is 94.19 dB, and the result of the circuit simulation with folded-cascode op-amp is 93.03 dB. The estimated PSNDR of the third-order multiple-feedback (MF) SDM with an OSR of 32 and a bandwidth of 256 KHz is 59.52 dB, and the HSPICE simulation result is 55.39 dB.

Introduction

Sigma-delta modulation (SDM) has become the most popular technique for high-performance analog-to-digital and digital-to-analog converters [1], [2], [3], and the trend of using mixed-signal integrated circuits has been growing rapidly in recent years. Fig. 1 illustrates a hierarchical top-down design flow for SDMs [4], [5]. Designers usually require much time to determine a suitable noise transfer function (NTF), fit the required coefficients, verify the stability of the system, acquire the specifications of the circuit and desired operational-amplifier (op-amp), and determine the transistor size of the op-amp. The design cycle is long and requires much experience. Thus, a computer-aided design (CAD) tool for SDMs is required for time to market and inexperienced designers. Many CAD tools have been developed and proposed, but the tools for the SDMs are either inefficient or incomplete. Thus, this creates a bottleneck during system-on-a-chip (SOC) design.

There are several studies that propose a complete solution for the automated design. An important study is proposed by Medeiro et al. [6]. They proposed a tool that starting from high-level specifications of SDMs calculates optimum specifications for their building blocks and optimum sizes for the block schematics. However, they did not provide the coefficient synthesis of the SDM architecture and use a set of simplified equations that led to a lack of accuracy. Furthermore, they only supported single-loop low-order SDMs and used a simulation-based approach to synthesize the size of the op-amp. The simulation-based approach requires more iterations and takes much time. For example, Medeiro et al. [6] mentioned that it takes 45 min to synthesize the folded-cascode op-amp.

Most of the studies are focused on the individual parts of SDM synthesis. Table 1 categorizes the previous works related to simulation tools, high-level synthesis, and op-amps synthesis. To shorten the simulation time, many efficient simulation tools have been developed to analyze and estimate the performance of SDMs. For example, ZSIM [7] integrates analytic tools, a difference equation simulator, a novel table-based non-linear z-domain simulator, and a digital signal processor into a workstation environment to provide fast and accurate simulations of SDMs. Previous works have shortened the simulation period of oversampling data converters, but the stability problem remains unsolved and without the concept of synthesis.

At the same time, some researches have focused on fast, efficient, and stable NTF synthesis for SDMs. For instance, Kenney and Carley [10] could be the first one to propose a high-level synthesis tool for SDMs. They developed a high-level synthesis tool, CLANS, which accepts SDM performance specifications and generates the optimal NTF from the block-level component specifications.

In [15], Kuo et al. proposed an empirical stability criterion and an automatic coefficients design for high-order SDMs. The stability upper bound of SDMs they presented could be determined by an empirical linear equation. Moreover, Schreier [13] also presented a coefficient synthesis tool containing several independent functions for designing an SDM. In recent years, research on topology synthesis has been proposed. Tang et al. [5] proposed a methodology for single-loop single-bit SDMs. The goal is to explore all possible topologies and to obtain the optimal topology under various design considerations, such as hardware complexity, modulator sensitivity, and power consumption.

After many studies on high-level SDM architecture synthesis, another research topic on the circuit specification synthesis was presented. Francken and Gielen [17] proposed a high-level simulation and synthesis tool for discrete-time SDMs based on a simulation-based optimization strategy. They overcame several limitations of the previous research, such as for only one topology, less precision, without non-ideal circuit consideration for circuit implementation, and a limited set of non-idealities. In addition, Ruiz-Amaya et al. [18] presented a high-level synthesis tool for SDMs that combines an accurate Simulink-based time-domain behavioral simulator with a statistical optimization core.

Research on op-amps synthesis is constantly in progress. It can be divided into three approaches: knowledge-based, simulation-based, and equation-based.

The knowledge-based approach adopts circuit design knowledge to construct the design rules. For example, IDAC [19] requires users to choose several basic circuit blocks with specific knowledge to implement the whole circuit. OASYS [21] divides the circuit into several basic blocks and simplifies the reuse of the design knowledge to design the whole circuit. However, because the second-order and short-channel length effects should be considered, these effects complicate the circuit design. Thus, the approach is not suitable for inexperienced circuit designers.

ECSTASY [22] and DELIGHT.SPICE [23] are the representatives of the simulation-based approach that commonly uses circuit simulators such as HSPICE [30] in each iteration. However, this approach can only find the local optimal solution; it requires more iteration and takes much time. The equation-based approach formulates the circuit characteristics using the equations in theory and solve these equations using some optimization algorithms. An optimization algorithm called geometric programming (GP) [31] has been adopted in recent years. Compared with the simulation-based approach, this approach has a global optimal solution. In [25], [26], [27], a design procedure of an op-amp with GP was proposed. Vanderhaegen et al. [28] modified the original GP into a reversed GP. It can improve the accuracy of op-amp synthesis, but the convergence rate becomes very slow. Moreover, to improve the accuracy, some of the previous works [29] combined the GP with a circuit simulator. By reducing the difference between the HSPICE results and the predicted results of GP, the predicted performance will be close to the specification.

Table 2 summarizes the characteristics of the three approaches. The knowledge-based approach is restricted due to the high demand of circuit knowledge and design experience. The simulation-based approach has the advantage of accuracy without much circuit knowledge, but the simulation time is considerable. Moreover, the equation-based approach improves the simulation time of the simulation-based approach, but it cannot realistically reflect the characteristics of the real circuits.

Aside from the coefficients synthesis of architecture for discrete-time SDMs presented in [32], this paper further proposes a complete solution for SDM design, including circuit specification synthesis and CMOS op-amp synthesis.

For circuit specifications synthesis, previous works have focused on op-amp finite gain, non-linearity, op-amp bandwidth, and slew-rate, separately. However, the non-ideal effects are highly correlated among one other. When integrating all non-ideal models, the final performance is much worse [33]. In this paper, all the effects are considered together for better accuracy. The finite gain and non-linearity of an op-amp are simulated first. The bandwidth and slew-rate of an op-amp are then modeled based on the op-amp finite gain and non-linearity. The circuit simulation results show that this method can predict the performance more accurately.

For op-amp synthesis, as simulation- and equation-based approaches have their own disadvantages in either speed or accuracy, a hybrid approach is proposed to improve both speed and accuracy. To estimate the transconductance (g_m) and drain-source conductance (g_ds) accurately, two modified models are introduced in the hybrid approach.

Consequently, a complete solution for automated synthesis of SDM is derived. The developed synthesis tool can rapidly synthesize an op-amp according to the required system specification. Even an inexperienced designer can design an SDM quickly with this proposed tool.

The paper is organized as follows. Section 2 shows the major non-ideal effects of circuit implementation; several behavioral models of these effects are created. Section 3 proposes a hybrid-based design methodology composed of simulation-based and equation-based approaches for synthesizing two-stage op-amps. In Section 4, an automated synthesis tool integrating coefficient synthesis, circuits specification synthesis, and op-amp synthesis is presented. Two design examples with different SDM architectures, specifications, and op-amps are given in Section 4.2. Finally, Section 5 concludes this paper.