BIST for network on chip communication infrastructure based on combination of extended IEEE 1149.1 and IEEE 1500 standards

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Abstract

In this paper we propose a BIST based method to test network on chip (NOC) communication infrastructure. The proposed method utilizes an IEEE 1149.1 architecture based on BIST to at-speed test of crosstalk faults for inter-switch links as well as an IEEE 1500-compliant wrapper to test switches themselves in NOC communication infrastructure. The former architecture includes enhanced cells intended for MAF model test patterns generation and analysis test responses, and the later architecture includes: (a) a March decoder which decodes and executes March commands, which are scanned in serially from input system, on First-In-First-Out (FIFO) buffers in the switch; and (b) a scan chain which is defined to test routing logic block of the switch.

To at-speed test inter-switch links one new instruction is used to control cells and TPG controller. Two new instructions, as well as, are applied to activate March decoder and to control scan activities in switch test session. These instructions are defined to fully comply with conventional IEEE 1149.1 and IEEE 1500 standards.

Introduction

Nowadays with advance in VLSI technology, designers are capable of embedding the components of a system in a single chip in the shape of functional and storage cores. These chips, called system on chip (SOC), can include series of heterogeneous components with irregular block sizes or homogeneous components with regular block sizes. SOC designing methodology, today has undertaken basic changes which is due to emergence of SOC platforms which support large complex of embedded cores [1]. In this type of chips, exchanging data between cores is done through a dedicated communication infrastructure (e.g. shared bus structure). Low scalability of the bus structures and increasing in chip operation complexity encountered designers with some limitations to embed numerous cores in SOCs. Therefore, a key requirement of these platforms, whether irregular or regular, is a structured communicational architecture. Network on chip (NOC) architectures were proposed as a holistic solution for a set of challenges faced by designers of large multi-core SOCs. Communication infrastructure for NOC includes switches and inter-switch links. Functional and storage cores connect to this infrastructure via network interfaces and exchanging data between cores is performed according a protocol.

Any new design methodology will only be widely adopted if it is complemented by efficient test mechanisms. The test strategy for NOC-based systems addresses three problems: testing the functional and storage cores and their corresponding network interfaces, testing the communication infrastructure itself, and testing the integrated system [2]. Since the inception of SOC designs, the research community has targeted principally the testing of the cores, giving little emphasis to the testing of their communication infrastructures. The main concern for SOC test was the design of efficient test access mechanisms (TAMs) for delivering the test data to the individual cores under constraints such as test time, test power, and temperature. Among the different TAMs, TestRail [3] was one of the first to address core-based tests of SOCs. With the appearance of the NOC architecture; recently, a number of different research groups suggested the re-use of the NOC communication infrastructure as a TAM [4], [5], [6], [7], [8], [9]. They assumed the communication infrastructure is fault-free and subsequently used it to transport test data to the functional blocks; however, for large systems, this assumption can be unrealistic, considering the complexity of the design and communication protocols. Therefore, developing a test strategy for NOC infrastructure itself is an important issue and must be addressed.

To test NOC infrastructure we are faced with testing the inter-switch links as well as testing the switches themselves. Due to existence of long inter-switch links in NOC infrastructure and rapid increase in the working frequency (currently in gigahertz range), signal integrity has become a major concern for design and test engineers. Use of nanometer technology in NOCs magnifies cross-coupling and mutual inductance effects among the link lines. This phenomenon, which is known as crosstalk, affects the integrity of a signal by adding noise and delay. Since it is impossible to predict the occurrence of defects that cause noise and delay, crosstalk testing is essential to ensure error-free operation of the chip and must be addressed in manufacturing testing. Also, the switch blocks consist of the FIFO buffers and the routing logic. FIFO buffers occupy more silicon area than routing logic and can be implemented as register banks [10] or dedicated SRAM arrays [11], so switch block testing breaks down into two problems: testing the FIFO buffers and testing the routing circuitry. Generally, routing logic consists of a few hundred logic gates, and engineers use traditional testing methods such as scan techniques. However, testing the FIFO buffers poses a unique challenge because many relatively small buffers are distributed all over the chip.

To carry test stimuli involving hundreds of chip inputs through many layers of chip to the lines which are implemented in ultra deep submicron (UDSM), and then convey the test results back through the many circuit layers to an observable point is very difficult. Therefore, we believe that one of the best choices to test inter-switch links is the boundary scan test methodology that includes the high capability of accessing lines of the link. The IEEE 1149.1 Boundary Scan Test standard [12], also known as Joint Test Action Group (JTAG) Standard, has been widely accepted and practiced in the testing community, and provides excellent testing features with low complexity. However, it was not intended to address at-speed testing of crosstalk faults. Therefore, we extended the IEEE 1149.1 boundary scan architecture to at-speed test of inter-switch links for crosstalk faults.

Some authors argue that the NOC switch is another IP core (flat or hierarchical) and its test can be defined using traditional core-based testing strategies [13], [14]. That is to say developing an IEEE 1500 test wrapper [15], [16] to test the switches can be a proper strategy. IEEE 1500 standard is widely used to test the core-based systems and provides the excellent feathers to test IP cores. Due to regular structure of NOC switches, especially their FIFO buffer structure, using all testing feathers of the standard imposes unacceptable area overhead; therefore we use some its feathers to develop a 1500-compliant wrapper to test the NOC switches themselves.

Maximum aggressor fault (MAF) model [17] is one of the fault models proposed for crosstalk. Various approaches to analyze the crosstalk are described in [18], [19], [20], [21]. There is a lot of possible design and fabrication solutions to reduce crosstalk effects on interconnects [22], [23], [24], [25], but none of them guarantee to resolve the issue perfectly. Therefore, several researchers have worked on test pattern generation for crosstalk. Attarha and Nourani [26] proposed a test generation method for signal integrity faults on long interconnects. Order reduction algorithm is used to generate test patterns in order to decrease execution time [27]. Five modified boundary scan adaptive algorithms for Wire–OR (W–0) interconnect fault of PCB interconnects was also proposed in [28]. Test generation for capacitance and inductance induced noise and delay on interconnects is studied in [29], [30], [31].

Several methodologies were proposed for testing crosstalk faults on long interconnects between cores in SOC [32], [33], [34]. Various issues on the extended JTAG architecture to test SOC interconnects for signal integrity are reported in [35], [36], [32], which use MAF and Multiple Transition (MT) Fault models.

Compared to traditional SOCs, test of NOC-based architectures involves multiple challenges due to the existence of complex network components [37]. Crecu et al. [38] tested NOC infrastructure (included inter-switch links and switches) in a recursive manner. They reduced test application time with using uni/multicast mechanism to test data transmission. In [39] a Built in Self Test (BIST) strategy has also been presented for NOC infrastructure. This BIST is carried out as a go/no-go BIST operation at start up, or on command. However, it has been proposed to use the NOC as a TAM during test of resources.

Aktouf [40] suggests the use of a boundary scan wrapper to test NOC components. The test includes the routers, the RAM blocks, and the embedded processors of the NOC architectures. Some researches have only focused on NOC switches. A test strategy for NOC switches based on IEEE 1500 standard was proposed in [41]. They reused FIFO buffers as boundary scan of the wrapper to test switching logic based on partial scan. Also based on partial scans, a strategy for testing of NOC switches has been proposed in [42]. With transient and intermittent faults becoming a dominant failure mode in modern VLSI, widespread deployment of online test approaches has become crucial. A number of test methodologies about this issue have also been presented in the literature [43], [44], [45]. They broadcast test vectors of MAF model [17] to all switches of a NOC structure by reusing communication links according routing algorithms and detects existing faults through comparison of switches outputs with each other.

A number of approaches to achieve fault tolerant NOC architectures have also been presented in the literature [46], [47]. Park et al. [46] discusses various types of reliability hazards in NOC structures and proposes a number of recovery techniques for reliability enhancement in presence of reliability hazards.

Lin et al. [48] design a scalable Built-in Self-Test/Self-Diagnosis (BIST/SD) architecture, Surrounding Test Ring (STR), to detect and locate faulty FIFOs and faulty MUXs for 2D-mesh based CMP systems. However, their method is limited to only regular 2D-mesh NOCs and cannot be implemented for various topologies (regular/irregular) of the NOC.

Nourmandi-pour et al. [49] proposed a test time effective method to test the inter-switch links based on IEEE 1149.1 standard. They provided at-speed test ability for IEEE 1149.1 standard to test interconnects by some minor changes performed in the standard's cells, and reduced test time application considerably. However, they targeted only the inter-switch links and disregarded the switches themselves.

Due to time nature of crosstalk effects, it must be tested with functional speed of chip. So proving at-speed test with high speed Automatic Test Equipment (ATE) for GHz systems is expensive, because it needs testers with capability of GHz. On the other hand, test data transmission from an ATE to lines which are embedded in systems so deeply needs a TAM which occupies unacceptable area overhead. Compared to these techniques, BIST is a proper method for testing at-speed of crosstalk faults because it eliminates the needs of expensive ATE.

To test the switch specially its FIFO buffers, BIST also is a suitable methodology, but one dedicated BIST per FIFO block would result in an unacceptably large silicon area overhead. Consequently, a distributed BIST methodology is more appropriate. In order to test routing block of the switch embedding one or more scan chains (depends on user choice) in routing logic can be a proper solution.

Our main contribution is test both inter-switch links and switches based on IEEE 1149.1 and 1500 standards, respectively, and integrate the tests in a BIST schema. One new instruction is used in IEEE 1149.1 architecture to at-speed test of crosstalk faults on the links as well as two new instructions are used to test the switches' FIFO buffers. The rest of this paper is organized as follows:

Section 2 describes fault models and their corresponding test patterns for inter-switch links and switches, as well as, test pattern generators to generate these test patterns. Section 3 gives the details of extended boundary scan cells capable of at-speed testing to test the links. Design a P1500-compliant wrapper to test the switches is brought in Section 4. Test architecture to apply test patterns and to receive test responses and to transfer test results out of chip is explained in Section 5. Simulation results including simulation and synthesis of proposed test architecture are discussed in Section 6. Finally, concluding remarks are in Section 7.

Section snippets

Fault models for NOC communication infrastructure

To develop a test methodology for NOC infrastructure, a set of fault models are required to sensitize and detect the faults specific to the nature of NOC infrastructure. As stated previously, an NOC infrastructure is built from two basic types of components: switches and inter-switch links. For each type of component, we must construct test patterns that exercise its characteristic faults. Following this section, we define fault models and test patterns which are capable of sensitizing and

Enhanced boundary scan cells to test NOC links

Boundary scan is a widely used test technique that requires boundary scan cells to be placed between each input or output pin and the internal core logic. The standard provides an efficient mechanism for functional testing of core logic and interconnects. Fig. 4 shows a conventional standard boundary scan cell (BSC). Cells on core primary inputs are referred to as “input cells”; cells on primary outputs are referred to as “output cells”. Mode=1 puts the cell in test mode. The data is

1500-Compliant wrapper to test NOC switch

To complement our test strategy discussed in Section 2.2.1, we briefly describe IEEE 1500 standard specially its wrapper serial port as well as an IEEE 1500-compliant wrapper to test NOC switches.

The standard defines a number of ports and registers. Two different ports are defined, the mandatory Wrapper Serial Port (WSP) and the optional Wrapper Parallel Port (WPP). The wrapper terminals in the WSP provide serial access to the IEEE 1500 wrapper. The WSP comprises ten terminals, eight mandatory

Test architecture for NOC infrastructure

Fig. 15 shows the overall test architecture with a link with N lines between two NOC switches. The five standard JTAG interfaces (TDI, TCK, TMS, TRST and TDO) and the ten WSP ports of the standard 1500 are still used without any modification. The interface logic is needed to connect IEEE 1500 wrapped switch, as shown in Fig. 15, into the IEEE 1149.1 architecture. The WSP terminals facilitate standard “plug and play” operation of the IEEE 1500 architecture. The mandatory part of the WSC part in

Simulation results

The proposed test architecture is simulated and synthesized using Mentor Graphic tools.

Table 5 shows the area overhead of 1149.1-TPG and its controller shown in Fig. 3. The total area overhead for conventional BSC cell and the enhanced BSCs, MPGBSC and RABSC for each of three response analyzing methods is shown in Table 6. Enhanced cells are 11–107% more expensive compared to the conventional one, that the most area increase is for RABSC in method 2. If one considers a pair of cells at

Conclusion

We have proposed BIST-based method for communication infrastructure of NOC. Our BIST based architecture detects crosstalk faults on the inter-switch links and tests the switches using combination of the widely used IEEE 1149.1 and IEEE 1500 architectures. To test the inter-switch links, minor modifications to conventional IEEE 1149.1 cells to generate MAF-patterns and to analyze test responses are needed. An IEEE 1500-compliant wrapper is also presented for each switch which receives test

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