A low-cost configurability test strategy for an embedded analog circuit
Introduction
Nowadays, microcontrollers (μCs) offer a broad pool of resources for performing a wide variety of operations, like signal conditioning, analog to digital conversion and digital signal processing. Modern μCs also include embedded analog configurable circuits (EACCs) that enhance the chip adaptation to different applications. The verification of the ability to program all the configurations available in the EACCs is very important for applications that require reliability, safe operation, adaptation to environmental changes or fault tolerance characteristics. The set of test procedures aimed to verify this configurability is referred to in this work as analog configurability test (ACT).
The test of EACCs is a challenge due to the particular characteristics of embedded systems. Some of them are the strong interaction between the digital and analog blocks and the usually high number of possible configurations. The former requires accessing the analog sections through a complex digital interface. The latter implies many different circuits to be tested.
Broadly, two different approaches could be applied for testing EACCs. The functional approach, or specification testing, accepts a circuit if all specifications are satisfied. The structural approach considers faults in the structure of the circuit and constructs test sets for detecting them based on measurements different from the specifications [1], [2], [3], [4]. For implementing a functional test approach, it is necessary to determine if all the functional parameters of the circuit under test (CUT) are within the specifications reported by the vendor. This requires the measurement of the EACC functional parameters for all the possible configurations. Therefore, the implementation of this approach would be extremely costly in both time and circuital resources. By the other way, a strictly structural test requires the transistor-level schematic of the CUT. However, the vendors usually provide only a simplified schematic just for understanding the module operation. This makes the approach difficult or impossible to apply in this kind of circuits.
In this work, we adopt an intermediate approach that consists in programming a reduced set of available configurations for the EACC and testing the block programmability by measuring a few key parameters. The limited structural information provided by the vendor is considered for simplifying the test procedures. Particularly, we address an EACC composed of operational amplifiers (OAs) and interconnection resources that are present in the MSP430x22x4μC family from Texas Instruments®.
This work is organized as follows. Section 2 discusses previous work related to the test of analog configurable circuits. In Section 3, a brief description of the MSP430 μC and general test considerations are presented. In Section 4, the implementation of the ACT approach is explained. The experimental results are reported in Section 5. Some ACT limitations are described in Section 6. Finally, Section 7 concludes the paper.
Section snippets
Previous work and paper contribution
A relatively low number of papers related to the test of analog configurable devices have been reported to the scientific community. The first efforts for applying known test techniques to the area of Field Programmable Analog Arrays (FPAAs) were made by Balen et al. [5], [6], [7]. In [5], the authors apply the oscillation-based test concept for testing configurable blocks of the ispPAC10 device from Lattice®. In [6], they propose a test response analyzer configured in the device and evaluated
Test considerations
The μC adopted as case study (MSP430F2274) is based on a 16-bit RISC CPU and includes several digital, analog and mixed-signal modules on-chip. The block diagram of the system, obtained from the datasheet provided by the vendor is depicted in Fig. 1. This figure shows the CUT (OAM0 and OAM1) and the blocks used by ACT highlighted.
The EACCs in the MSP430 are the so-called OA modules (OAM0 and OAM1 in Fig. 1) [18]. An OA (OAx), several analog multiplexers (MUX), a resistor ladder and other
Analog configurability test scheme
The embedded test routine mainly performs three different tasks. The first one tests the voltages of the resistor ladder, the second one tests the configurability of the all available modes by programming selected gains and the third one verifies the configurability of the slew rate in each OA. The test routine does not exercise mode 1 because the μC has only two OAMs, and the vendor recommends this mode for implementing a three-OA differential amplifier configuration [19].
As shown in Fig. 2,
Experimental test results
The test routine has been written in C language using IAR Embedded Workbench for TI MSP430 C/C++ compiler and amounts to about 1 kbyte of program memory in the μC. The experiments were performed in a TI eZ430-RF2500 board, a complete USB-based MSP430 wireless development kit that provides the necessary hardware to evaluate the MSP430F2274 μC. For the device chosen in this work, the total routine execution time is 16.3 ms with a CPU clock (Master clock, MCLK) of 1 MHz.
First, we evaluate the
Acceptance range for the resistor array and gain values
The measurements performed by ACT present errors attributed to the ADC inaccuracies. The total unadjusted error determines the overall deviation of the digital code from ideal. This error includes offset, gain, and nonlinearity errors in its calculation. The datasheet quotes a typical value of ±2 LSB for the total unadjusted error with a maximum of ±5 LSB equivalent to ±17.733 mV for our test conditions. This value is considered here as the limiting error of the voltage measurements (ΔV),
Conclusions
The main goal of this paper is the development of a test strategy for EACC that employs only internal resources of the MSP430 μC. The proposed scheme allows establishing the correct configurability of the CUT and checks the proper behavior of the resistor arrays. The negligible hardware overhead of the test scheme allows using it in applications that require minimizing power or cost. Additionally, due to the modularity of the scheme, some steps involved in the test can be avoided for reducing
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