A 15fJ/conversion-step 8-bit 50 MS/s asynchronous SAR ADC with efficient charge recycling technique

Abstract

An 8-bit successive approximation analog-to-digital converter (ADC) with small area and high power efficiency is presented in this paper. The proposed ADC includes digital foreground calibrated comparator and a novel capacitor switching method. The former one uses programmable voltage coming from resistive divider to control the bulk of latch input differential pair, therefore comparison speed does not need to compromise and the nonlinearity introduced by variation of input capacitance is reduced. The latter one utilizes two separated capacitor arrays in a post-comparison and binary tree manner so as to save power consumption of charge recycling. Moreover, asynchronous timing control and reference-free architecture is implemented to further decrease the power and simplify auxiliary circuits for ADC. It is designed in a 65 nm digital CMOS process, achieving 49.9 dB signal-to-noise-and-distortion-ratio (SNDR) and 72.0 dB spurious-free-dynamic-range (SFDR) at the sampling rate of 50 MS/s while consuming 192.8 μW from 1 V power supply. The figure of merit is as low as 15fJ/conversion-step.

Introduction

A wireless sensor network (WSN) is made up of a large number of sensor nodes that are typically small in size and battery-operated. Thus, low-power and low-cost design is the key requirement for a WSN node [1]. The analog-to-digital converter (ADC) is one of the critical components in designing such a sensor node IC since it dominates both the power consumption and the die size [2], [3]. Besides the ADC core itself, its associated circuits including reference voltage generator, reference current generator and sampling clock generator are also of major concerns in a low-power design.

Based on system requirements of spectrum and signal bandwidth, Successive-Approximation-Register (SAR) has been considered as one of the power efficient ADC structures for a WSN node. In general, SAR ADC is superior to Nyquist sampling ADC such as flash ADC and pipeline ADC mainly due to the fact that its power consumption is a linear function of the output resolution while flash or pipeline ADC acts as an exponential function. In addition, SAR ADC is small in geometry and its structure is high-gain amplifier-free. Furthermore, SAR ADC is compatible with the standard CMOS process with low supply voltage, which makes it possible to shrink the device dimension to 65 nm or smaller. The design would then benefit from technology scaling and from high speed, low parasitic, small area, low voltage and low power operations. As a result, there have been plenty of works reported about SAR ADC to improve its power efficiency using a variety of techniques over past few years [4], [5], [6], [7], [8], [9], [10]. The design enhancements have been focused on three areas: charge recycling [4], [6], timing control [5], [10] and comparator structure [7], [8]. The best figure of merit (FOM) was achieved as low as 4.4fJ/conversion-step [2].

This paper presents an asynchronous SAR ADC design that combines several enhancement techniques to achieve high power efficiency. Firstly, an auxiliary capacitor array is used to generate comparison levels for more efficient charge recycling. Secondly, a digital foreground calibration algorithm is implemented for the smaller comparator input capacitance to improve its linearity. In this algorithm, the feedback path has no negative effect to the comparison speed or the power consumption, and the proposed nonlinear resistor spread improves the calibrated comparator offset over the conventional linear one. Finally, a reference-free structure serves as the outside reference generator and the voltage buffer, and an asynchronous timing control logic eliminates the oversampled system clock.

This paper is organized as follows: Section 2 illustrates the architecture of the proposed SAR ADC; Section 3 describes in detail the circuit implementation and the digital algorithm; the simulation results and the conclusions are provided in 4 Simulation results, 5 Conclusion, respectively.