Passive mixer with OPA filter for DVB-H front-end in 65 nm digital CMOS technology
Introduction
Digital Video Broadcast for Handheld (DVB-H) is a mobile television standard based on Digital Video Broadcast for Terrestrial (DVB-T). It is specifically designed for mobile devices like mobile phones. Due to the fully backward compatibility to DVB-T, the already existing infrastructure can be used and a large geographical area can be reached with the signal. DVB-H is a point-to-multipoint connection in contrast to UMTS which is a point-to-point connection. The multipoint approach offers the advantage of high data throughput to multiple consumers at the same time while only occupying a small frequency spectrum for transmission [1].
For mobile receiving devices, low power consumption is a very important aspect. Furthermore such systems need to be fully integrated in one technology. Integration of the entire receiver in one technology reduced fabrication costs as only one set of masks has to be fabricated and it also reduces parasitic elements which arise when multiple integrated circuits are connected together. These are inductances from bond wires and capacitances from bonding pads. Fig. 1 shows the block diagram of a direct I/Q conversion receiver [2] which is the preferred implementation for such fully integrated receiver systems. It consists of an antenna and usually some sort of band-pass filter. In the diagram a surface acoustic wave (SAW) filter is indicated because such filters have superior performance at high frequencies compared to active filters. As close to the antenna as possible a low noise amplifier (LNA) is placed to amplify the signal for further processing in the receiver chain. After the first amplification two separate signal chains, the inphase (I) and quadrature (Q) chains are placed. With this technique digital image rejection is achieved. After down-conversion of the signal into the baseband, a low-pass filter limits the bandwidth of the received signal to 4 MHz. This 4 MHz is the channel bandwidth of the different DVB-H channels. After the filtering, an analog to digital converter (ADC) converts the signal into the digital domain where the baseband processing can be performed in a digital signal processor (DSP) or microprocessor.
Section snippets
Circuit overview
We implemented a passive mixer in combination with a first order low-pass filter for one of the direct conversion receivers. Fig. 2 shows the block diagram of a test chip with the passive mixer in combination with the filter. The test chip has an additional circuit block, the clock regeneration circuit, which is needed for characterization by measurement. This clock regeneration circuit is used for reshaping the applied differential clock to a full logic swing. For operation of the passive
Clock regeneration circuit
The clock regeneration circuit is needed to have a full swing digital signal for the switching transistors in the passive mixer circuit. With a better switching characteristic, also the performance parameters of the entire circuit increases. To avoid the need for a very large differential clock signal at the input, the signal is rectified directly on chip with the circuit show in Fig. 3. A differential signal LOin is applied at the input to the two cross-coupled inverters which consists of the
Passive mixer circuit
The passive mixer relies on the gm-cell to provide a current signal for down-conversion. The schematic of this circuit part is shown in Fig. 5. A biasing circuit provides a DC-bias for the two input transistors M1 and M2. The bias condition can be externally adjusted with an applied DC current through transistor M3. The resistor R1 and capacitor C1 are added to the current mirror to suppress noise and other unwanted spectral components from the external bias pin.
For the amplifier itself,
Measurement results
The designed test chip was fabricated in a 65 nm digital low-power CMOS technology by Infineon Technologies Austria AG. The test chip was characterized in the laboratory. To achieve the best performance in the measurement setup, the bare die was directly bonded to a gold plated printed circuit board (PCB). The high frequency inputs are terminated with 50 Ω resistors on chip and the PCB uses matched microstrip lines to eliminate reflections in the measurement setup. The entire chip including
Conclusions
A direct down-conversion receiver front-end in 65 nm CMOS technology with a very low flicker noise corner frequency of 80 Hz was presented. This low flicker noise corner frequency is currently the lowest mentioned in literature. The passive mixer in combination with an active 1st-order low-pass filter achieves a conversion gain of 26 dB while consuming a total of 16.6 mA from a 1.25 V supply. The linearity measurements show a 1 dB-compression point of −16 dBm and an IIP3 of −5 dBm. The low-pass
Acknowledgment
The authors would like to thank Infineon Technologies Austria AG for partially funding the work. Furthermore the funding from the Austrian Federal Ministry for Transport, Innovation and Technology in the FIT-IT project M2RX via FFG is gratefully acknowledged.
References (9)
- et al.
DVB-H and IP datacast—broadcast to handheld devices
IEEE Trans. Broadcast.
(2007) - et al.
Receiver I/Q imbalance: tone test, sensitivity analysis, and the universal software radio peripheral
IEEE Trans. Instrum. Meas.
(2010) - et al.
Analog circuits in ultra-deep-submicron CMOS
IEEE J. Solid-State Circuits
(2005) - H. Uhrmann, H. Zimmermann, A fully differential operational amplifier for a low-pass filter in a DVB-H receiver, Int....
Cited by (2)
A SiGe:C BiCMOS dual down converter for MIMO wireless infrastructure with configurable current consumption and linearity
2018, Analog Integrated Circuits and Signal ProcessingCMOS harmonic upconverter with power management of 2 nd harmonic for wideband short-range communications
2017, Analog Integrated Circuits and Signal Processing