Elsevier

Microelectronics Journal

Volume 44, Issue 10, October 2013, Pages 953-958
Microelectronics Journal

Closed-form expressions for the coupling capacitance of metal fill tiles in VLSI circuits

https://doi.org/10.1016/j.mejo.2012.11.001Get rights and content

Abstract

A new closed-form formula for the computation of the coupling capacitance of metal tiles is presented in this work. It exploits the analytical solution of the Laplace equations of equivalent studied problems. Comparative results are given with two commercial tools employing the boundary element method (BEM) and the finite element method (FEM). The results show that the capacitance value computed by the proposed formula is in close agreement to the value obtained by the simulators.

Introduction

The rising demand for full system integration on a single chip has led to the continuous increase in the integration density. Multiple metallization layers have been added recently whereas the total thickness of the oxide has been significantly increased leading to mechanical stress issues. To avoid chip bending of even fracture, a solution that has been emerged is the use of dummy metal tiles, Fig. 1. In modern technologies, every chip area that it is left empty of metallization by the designer is automatically filled with metal tiles [1], [2], [3], [4], [5], [6], [7], [8], [9].

Although metal tiles provided a solution to mechanical stress problems new problems have aroused [1], [2], [3]. Since tiles are consisting of metals they are capacitively coupled with other devices in the chip. An undesired effect of metal tiles is the increase of the parasitic capacitive coupling of a device to the backplane of the chip. This may lead to a degradation of the performance of the device, for example it may reduce its frequency range or influence its power consumption. Metal tiles may also have an impact to the delay characteristics of a signal line. The use of tiles is not an option but in most cases it is enforced (few foundries offer a tile exclude option). For this reason and also because the dummy fill is typically inserted at the tape-out phase, the correct prediction in the design phase of the metal tiles to the device or the interconnect line becomes imperative.

The metal tiles may be floating or grounded. Although the latter scheme is more stable and easy to extract it is not preferred due to its higher impact on capacitance and also because multiple ground connections are necessary to provide the ground path to the dummy pattern [1], [5], Therefore, the current study will focus on the floating dummy metal fill. Typically, the additional coupling that is due to the tiles block, may be modeled by a lumped capacitance element describing the coupling of the tiles block to the backplane of the chip.

The extreme complexity of the dummy fill introduces great difficulties to the accurate modeling of its coupling capacitance [1], [5]. Currently, the correct prediction of the impact of tiles to a device is only possible through the numerical solution of the electromagnetic (EM) equations that describe the problem. The most common methods for this purpose are the finite element method (FEM) and the boundary element method (BEM). However, these methods are slow due to the increased complexity of the problem while in some cases, e.g., when the dimensions of the tiles are very small in comparison with the rest structures, they even fail to converge to a solution. Thus, closed-form or empirical formulae are preferred.

Although a few studies have been presented and empirical formulae have been reported [1], [2], [3], [4], [5], [6], [7], [8], [9], these are either derived for very simple cases, e.g., [6] for a MIM capacitor, or they are based on fitting techniques based on results obtained mostly from simulations. For this reason, these formulae are process dependent and their range of validity is limited. To the best of the authors' knowledge an exact formula describing the additional capacitive coupling introduced by the tiles block has yet to be reported. In this work, a closed-form formula is proposed for the computation of the impact of the metal tiles on the device under test. The formula is exact in the sense that it is derived by the analytic solution of the equations that describe the problem and neither fitting techniques nor empirical formula are used at any step of the derivation procedure. For the final solution, the initial problem is transformed to an equivalent already studied problem of heat transfer.

This work is organized as follows. In Section 2 the problem formulation is described and the exact formula is derived. The formula is then validated with simulation data in Section 3. Finally, Section 4 concludes this work.

Section snippets

Problem formulation

In modern technologies, any free of metal region is filled by default with dummy metal tiles, as illustrated in Fig. 1. Various patterns are used by different foundries as shown Fig. 2, but they all share a common feature. The geometric shapes of the tiles consist mostly of squares and rectangles. The typical dimensions of these shapes vary from about 5 μm to 1 μm or even less.

In this work, every tile pattern is segmented to a finite number of squares. Then every square is approximated with a

Simulation results

The proposed formula for the computation of the coupling of metal tiles has been studied in several test cases encountered in practice. The results have been compared with the simulation data obtained by two commercial simulators namely COMSOL [17] employing a FEM method and Agilent ADS [18] which utilizes a BEM method. Any difference observed between the results based on the proposed formula and the results from the simulators may be attributed to the two approximations introduced in this

Conclusions

A closed-form formula is presented for the computation of the capacitive coupling of dummy metal tiles and their impact on other structures. It is obtained by an equivalent problem for which an analytical solution already exists. The proposed approach is faster than the electromagnetic methods whereas it can succeed the same level of accuracy. Comparative simulation results as obtained by two commercial tools show a close agreement with the proposed formulation suggesting its validity.

Acknowledgement

This research is co-financed by Hellenic Funds and by the European Regional Development Fund under the Hellenic National Strategic Reference Framework 2007–2013, according to Contract no. MICRO2-47 of the Project “Next Generation Millimeter Wave Backhaul Radio” within the Programme “Hellenic Techonology Clusters in Microelectronics - Phase-2 Aid Measure”.

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