Elsevier

Microelectronics Journal

Volume 44, Issue 12, December 2013, Pages 1052-1062
Microelectronics Journal

Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA

https://doi.org/10.1016/j.mejo.2012.12.010Get rights and content

Abstract

An Application Specific Inflexible FPGA (ASIF) is a modified form of an FPGA which is designed for a predefined set of applications that operate at mutually exclusive times. An ASIF is a compromise between FPGAs and Application Specific Integrated Circuits (ASICs). Compared to an FPGA, an ASIF has reduced flexibility and improved density while compared to an ASIC, it has larger area but improved flexibility. This work presents a new homogeneous tree-based ASIF and uses a set of 16 MCNC benchmarks for experimentation. Experimental results show that, on average, a homogeneous tree-based ASIF gives 64% area gain when compared to an equivalent tree-based FPGA. Further, the experiments are performed to explore the effect of look-up table (LUT) and arity size on a tree-based ASIF. Later, comparison between tree and mesh-based ASIF is performed and results show that tree-based ASIF is 12% smaller in terms of routing area and consumes 77% less wires than mesh-based ASIF. Finally the quality comparison between two ASIFs reveals that, on average, tree-based ASIF gives 33% area gain as compared to mesh-based ASIF.

Introduction

Medium to low volume production of FPGA-based systems is quite effective and economical because FPGAs are easy to design and program in shortest possible time. However, the generic reconfigurable resources of FPGAs lead to larger area, poor performance and higher power consumption as compared to ASIC. As a result of these drawbacks, FPGAs become unsuitable for applications requiring high density, good performance and low power consumption. To address this limitation a range of alternatives to FPGAs exist.

The primary alternative to an FPGA is an ASIC that has better speed, power, and area results compared to an FPGA. However, ASIC design requires huge resources in terms of time and money and their design complications have significantly increased with advancement in process technology. These complications have led to the development of structured-ASICs which can cut the Non Recurring Engineering (NRE) cost of ASICs by more than 90% and speed up significantly their time to market [1]. Structured-ASICs have gained popularity in a short time and they are now manufactured by several companies [1], [2], [3], [4]. FPGA vendors have also started giving provision to migrate FPGA based application to structured-ASIC [5] while ensuring equivalence verification between FPGA and its structured-ASIC [6]. However, migration of an FPGA based application to structured-ASIC can execute only a single circuit and it totally loses the quality of reconfigurability.

An ASIF [7], on the other hand, composed of optimized logic and routing resources like structured-ASIC but retains enough flexibility to implement a set of pre-determined applications that operate at mutually exclusive times. An ASIF can give considerable area, performance and power gains to an FPGA-based product by reducing it to a much smaller multiplexed circuit. Execution of different application circuits can be switched by loading their respective bitstream on ASIF. But, generation of an ASIF from an FPGA makes its architecture irregular; hence making its layout more difficult as compared to FPGA. Although the effort required for the layout of ASIF is comparatively less than that of ASIC, it will occupy more area than ASIC. Also commercial synthesis tools can be used to generate a standard cell based ASIC that can execute multiple application circuits at mutually exclusive times. However, contrary to ASIF, commercial tools used to automatically generate ASICs are unable to exploit the resources shared by the circuits [8]. Also, unlike an ASIF, an automatically generated ASIC is less probable to repeatedly use hardware components like LUTs; hence full custom layout of repeatedly used cells is not viable for ASICs. In this work, we present a new homogeneous tree-based ASIF. A preliminary version of this work was initially presented in [9] which is extended here and new results are added to add depth to already presented results.

The remainder of the paper is organized as follows: Section 2 gives a brief overview of the mesh- and tree-based FPGA architectures. Section 3 describes the associated software flow of two architectures. Later these FPGA architectures are reduced to their respective ASIFs. Section 4 details ASIF generation technique and Section 5 presents the area model used for ASIF area calculation. Section 6 presents experimental results and Section 7 finally concludes this paper and presents some future work.

Section snippets

Reference FPGA architectures

In this work, we consider two types of FPGA architectures: one is mesh-based while other is tree-based. Different benchmarks are mapped on these FPGA architectures and later they are reduced to their respective ASIFs. Both mesh- and tree-based FPGA architectures composed of similar logic and routing resources. However, it is the arrangement of these resources that separates the two architectures. In a mesh-based architecture logic resources are arranged in a two-dimensional grid and routing

Software flow

It is well established that the quality of an architecture is largely dependant on the accompanying software flow that is used to map different benchmarks on the architecture. Benefits of an otherwise well designed architecture might be affected if the CAD tools cannot take full advantage of the features provided by the architecture. Since in this work we are considering two architectures, we have specifically designed two software flows for both architectures where some parts of the flow are

ASIF generation

Reconfigurability of FPGAs is their biggest asset but at the same time it is also their largest drawback. Customized reconfigurable architectures like ASIF can reduce the overheads of FPGA while maintaining a certain degree of flexibility. An ASIF is reduced from an FPGA where all unneeded reconfigurability is removed. In order to generate an ASIF, first, a common FPGA architecture is defined that can implement any of the applications of the set. Netlists are then individually placed and routed

ASIF area model

A generic area model is used to calculate the area of different ASIFs and this model is applicable to both mesh- and tree-based ASIFs. The area model is based on the reference mesh- and tree-based FPGA architectures explained in Section 2. Netlists are efficiently placed and routed on the FPGA architectures using the techniques described in the previous section and later unused resources are removed to generate ASIF. In Ref. [21], authors have revealed that transistor area, and not wiring

Experimental results and analysis

Efficient logic and routing resource sharing techniques explained in Section 4 are integrated to their respective algorithms to efficiently generate mesh- and tree-based ASIFs. For experimental purposes, a set of 16 MCNC benchmarks [24] is used where mesh- and tree-based ASIFs are generated for these benchmarks using the techniques described in the previous section. Details of these benchmarks are shown in Table 2 where each benchmark is shown having specific numbers of inputs, outputs, and

Conclusion

In this work, a new homogeneous tree-based ASIF is presented. This work is basically an attempt to explore the design space between FPGA and ASIC. In this work we have explored different ASIF generation techniques using a total of 16 MCNC benchmarks. Comparison of different techniques with equivalent tree-based FPGA shows that the most efficient ASIF generation technique is 64% smaller than an equivalent tree-based FPGA. Further the exploration of LUT and arity size on tree-based ASIF shows

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