Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects

Abstract

This research work presents a novel circuit for simultaneous reduction of power, crosstalk and area using bus encoding technique in RC modeled VLSI interconnect. Bus-invert method is used to reduce inter-wire coupling, which is actually responsible for crosstalk, delay and power dissipation in coupled interconnects. The proposed method focuses on simplified and improved encoder circuit for 4, 8 and 16 coupled lines. In past, the researchers developed encoders that usually focused on minimizing power dissipation and/or crosstalk, thereby paying heavy penalty in terms of chip area. However, the proposed encoder and decoder while significantly reducing crosstalk demonstrates an overall reduction of power dissipation by 68.76% through drastically limiting switching activity. Furthermore, while reducing the complexity, chip area and transistor count of the circuit is reduced by more than 57%.

Introduction

In deep submicron VLSI design, feature size will continue to shrink while the clock frequency will keep on increasing rapidly. In case, the current trend of technology scaling continues, the devices and gates would be much smaller and faster [1], [2]. However, the interconnect delay is expected to increase, therefore, interconnect delay will dominate over gate delay [2]. Shrinking feature size implies not only shorter gate lengths but also decreasing interconnects pitch. Hence, minimizing the power consumption and crosstalk delay in interconnects is the most important design criteria in on-chip bus design [3], [4], [5]. These effects are dominated by coupling capacitance and load capacitance. Load capacitance is the capacitance between wire and the substrate. The capacitance between the two interconnects which are adjacent is called coupling capacitance. This capacitance causes crosstalk, leads to serious timing and signal integrity problems and results in circuit malfunctioning in the worst case. It affects delay and slew depending on the switching configurations of aggressor and victim lines.

There are different methods such as repeater insertion [6], shielding line ($V_{dd}$/GND) insertion between two adjacent wires [7], optimal spacing between signal lines and lastly the most effective bus encoding method [8], [9], [10] for reducing the crosstalk delay. A bus encoding method converts or encodes the data bit stream in such a way that the number of transitions of bit stream is minimized.

This paper focuses on reducing power dissipation, crosstalk and chip size of the encoder and decoder by using bus-invert method [9]. This method reduces power and crosstalk delay by decreasing switching and coupling activities. The proposed method eliminates the most undesirable crosstalk types in RC coupled interconnects i.e. Type-4, Type-3 and some of the Type-2 couplings. Results show that the power dissipation, crosstalk, delay are reduced and the size of the encoder implemented occupies lesser chip area as compared to Fan et al. [12].

The paper is organized in six sections including the current section pertaining to Section 1. Section 2 describes the classification of crosstalk, whereas, Section 3 comprises of power dissipation expression and their dependence on different parameters. The functioning of proposed encoding method is explained in Section 4. Sections 5 discusses the experimental results of proposed RC encoder. Finally, in Section 6 important outcome of the proposed encoder design is summarized.