Temperature dependent timing in standard cell designs

doi:10.1016/j.mejo.2013.08.016

Microelectronics Journal

Volume 45, Issue 5, May 2014, Pages 521-529

https://doi.org/10.1016/j.mejo.2013.08.016 Get rights and content

Abstract

This paper proposes a methodology to simulate temperature dependent timing in standard cell designs. Temperature dependent timing characteristics are derived from standard delay format (SDF) files that are created by synthesis tools automatically based on SPICE characterizations. In addition, a fast calculation of temperatures using the equivalent Foster RC network is presented. A case study is also presented in this paper where the temperature dependent frequency variation of a ring oscillator is simulated demonstrating the necessity of temperature dependent timing simulations. An adaptively refineable partitioning method for simulating standard cell designs logi-thermally is proposed as well. This paper also introduces recent enhancements in the CellTherm logi-thermal simulator developed in the Department of Electron Devices, BME, Hungary. Finally, the simulation results are compared and verified with the SPICE compatible ELDO analog simulator from Mentor Graphics.

Section snippets

Introduction and motivation

In today's digital integrated circuits dealing with heating issues became a primary concern. As technology nodes and minimum feature size (MFS) keep shrinking device parameters tend to become more sensitive to process variations, supply voltage fluctuations and device temperature, to mention a few. These phenomena inferred the need for a simulation tool which is aware of process, temperature and supply voltage variations and can detect issues caused by such effects. A simulation framework is

Related work

In [1] Pable et al. deal with ultra-low-power signaling challenges caused by process, voltage and temperature (PVT) variations. Exponential dependency of subthreshold drive current on V_th and temperature in subthreshold operating region makes process and temperature variations of great interest while designing robust ULP systems. Small variation in the device V_th will translate into exponential variation in bias current and hence the device delay and power dissipation. The subthreshold

Design for demonstration

Our case study was a 0.516 mm×0.353 mm standard cell digital circuit with four buffer cells driven with a 4-bit digital counter stimuli and a ring oscillator circuit. The process node was TSMC $0.35 μ m$ . The design has been created from a synthesized Verilog description. For automated placement and routing Pyxis was used from Mentor Graphics^©. This design was created in order to demonstrate the effect of temperature variations and evolving hot-spots on cell propagation delay. Cell delays and power

Grid partitioning

In CellTherm the surface of the standard cell IC can be divided into subregions called partitions where dissipated powers are accumulated and temperatures are calculated. The partitioning approach speeds up simulation times and initial database parsing in large designs containing more than 1000 standard cells. This approach makes the initial thermal model generation practically insensitive to the number of standard cells. Of course logic simulation can take longer for designs containing high

Power and temperature distribution

Fig. 4 depicts the power distribution of the design. In our test case, the BUFFER cells are driven in a counter-like pattern, that is, switching activity of the flip-flop chain can be specified as $A (xbuf 4) = 2 \cdot A (xbuf 3) = 4 \cdot A (xbuf 2) = 8 \cdot A (xbuf 1)$ where $A ()$ means the switching activity of the cell. The dissipated dynamic power per logic transition is proportional to the switching activity.

In the power map it can be seen that due to the evenly distributed layout, the power dissipation spreads evenly in the

Data serialization

The initial database for the logi-thermal simulation is generated from the LEF/DEF layout files, Liberty .lib files, and SDF files. In a design with thousands of standard cells this initial database creation can take hours to complete. For example, in a design containing 1490 cells manufactured on a 65 nm STMicroelectronics process the initial database generation and the thermal model generation took 56 min. This initial process of internal database creation and thermal model generation has to be

Thermal model generation

In this section we describe the steps needed to create the thermal RC model of microelectronics structures. Fig. 6 shows a typical structure of an integrated circuit.

1.
In an integrated circuit like depicted in Fig. 6, different structure parameters are required for generating the thermal RC model. These parameters are
- $•$
  lateral size of the structure (width, height),
- $•$
  width of layers,
- $•$
  material parameters of the layers (heat transfer coefficient, heat capacity),
- $•$
  boundary conditions (adiabatic, isothermal,

Equivalent thermal RC network calculation

CellTherm determines the power dissipated by the standard cells using the switching activity extracted from the logic simulator, and the Liberty power database. This power heats up the device during operation. In the beginning of the simulation CellTherm builds the equivalent thermal representation of the device in terms of an RC network. It does this from the layout data, the position of the cells on the surface and the layer structure. Due to the fact that thermal resistances and thermal

Temperature-delay functions

The temperature dependent delays of the standard cells can be calculated using the SPICE simulations of the cells. These measurements provide the most accurate temperature-delay functions but the simulated cells given by transistor-level netlists do not contain layout data. Propagation delay of standard cells depends strongly on placement and wiring.

Temperature-delay functions for the placed and routed design can also be calculated from synthesizer-generated SDF files. SDF files contain timing

Temperature dependent delay simulation

In the test vehicle showed in Fig. 1 the temperature-dependent frequency variation of the ring oscillator is demonstrated. By the self-heating of the ring oscillator's inverters and the dissipation of the buffer cells, the temperature distribution on the IC surface will not be uniform thus each inverter cell in the ring oscillator will have a different propagation delay. The delays are calculated from the standard cell's current temperature and updated in every simulation time step. The varying

Results

Temperature curves versus simulation time for the xinv5, xnand and xnand cells is shown in Fig. 16. It can be observed that the circuit reaches steady-state temperature near the 4th second. The temperatures throughout this paper are differential not absolute temperature values.

In Fig. 17 the period and the frequency of the ring oscillator are depicted versus simulation time. It is clearly visible that with the increasing simulation time the temperature also rises thus the period of the ring

Assessment and validation

The CellTherm simulations have been verified with several approaches. From the SPICE simulation of the transistor-level netlist of the design, the dissipations and delays of the cells have been extracted. Dissipation and timing data could have been also extracted from a Liberty database of the process. A Liberty file in our process node (TSMC $0.35 μ m$ ) was not present, so we needed to extract the parameters from SPICE simulations manually (Liberty databases claim to be inside 2% of accuracy

Summary and conclusion

In this paper a methodology for simulating temperature dependent propagation delays in a ring oscillator circuit is demonstrated. A special demonstration circuit has been created to spectacularly demonstrate the effect of circuit self-heating on propagation delays and operating frequency.

Temperature dependent delays are calculated from synthesizer-generated SDF files making thermal-aware logic simulations possible.

A grid partitioning method has been introduced where the created thermal model is

Acknowledgment

This work was partly supported by the IP 248603 THERMINATOR FW7 project of the European Union and by the Hungarian Government through TÁMOP-4.2.1/B-09/1/KMR-2010-0002. I would like to thank Dr. Vladimir Szekely for his consultation and very useful help as well as for some program parts in the CellTherm application.

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Temperature dependent timing in standard cell designs

Abstract

Section snippets

Introduction and motivation

Related work

Design for demonstration

Grid partitioning

Power and temperature distribution

Data serialization

Thermal model generation

Equivalent thermal RC network calculation

Temperature-delay functions

Temperature dependent delay simulation

Results

Assessment and validation

Summary and conclusion

Acknowledgment

Integration, The VLSI Journal

Microelectronics Journal

Integration, The VLSI Journal

Microelectronics Reliability

Microelectronics Reliability

Microelectronics Reliability

Microelectronics Journal

Reversed temperature-dependent propagation delay characteristics in nanometer CMOS circuits

IEEE Transactions on Circuits and Systems IIExpress Briefs