Elsevier

Microelectronics Journal

Volume 45, Issue 2, February 2014, Pages 167-178
Microelectronics Journal

Design and verification of a frequency domain equalizer

https://doi.org/10.1016/j.mejo.2013.10.012Get rights and content

Abstract

In this work we provide a methodology for the design and verification of a frequency domain equalizer. The performance analysis of the equalizer is conducted using two methods: simulation based verification in Simulink and System Generator and theorem proving techniques in Higher Order Logic. We conduct both floating-point and fixed-point error estimations for the design in Simulink and System Generator, respectively. Then, we use formal error analysis based on the theorem proving to verify an implementation of the frequency domain equalizer based on the Fast LMS algorithm. The formal error analysis and simulation based error estimation of the algorithm intend to show that, when converting from one number domain to another, the algorithm produces the same values with an accepted error margin caused by the round-off error accumulation. This work shows the efficiency of combining simulation and formal verification based methods in verifying complex systems such as the frequency domain equalizer.

Section snippets

Introduction and motivation

With the recent technological growth, electronic devices have invaded all aspects of our lives. These devices are getting more and more compact and consequently more complex. The price of this complexity is the challenge of delivering error-free devices, which require thorough testing and verification at all stages of the design flow. On the other hand, a faulty design can lead to costly delays for the time-to-market. Therefore, design verification is necessary to avoid such situations and is

Related work

The design and implementation of frequency domain equalizers is considered vital since equalization is a fundamental process in modern communication systems. Wang et al. [8] presented an iterative frequency–time domain equalizer for Advanced Television Systems Committee (ATSC). In this approach, the multipath distortion in the signal is first compensated with a frequency domain equalizer on a block-by-block basis. Then, a time domain interference cancelation algorithm is used to eliminate the

Frequency domain equalizer

Data alteration between the frequency domain and the time domain requires the use of some tools ensuring the preservation of data during this transition. The most useful tool enabling representation of a signal in the frequency domain is the discrete transform that helps to decrease the computational complexity related to signal processing just like convolution. The Discrete Fourier Transform (DFT) is used for the conversion of a discrete signal from the time domain to the frequency domain.

The

Problem definition

To decrease the filtering complexity, an equalizer can be implemented in the frequency domain using the Fast Fourier Transform (FFT) and Inverse FFT (IFFT), where time convolution is replaced by frequency multiplication. This method offers low complexity growth in comparison with the time domain method. Data processing and filtering requires dealing with data at different domains: real number, floating-point number, and fixed-point number domains. The specification of an equalizer design can be

Design and verification methodology

In order to achieve a certain level of assurance we use a theorem proving based verification in order to provide formal error analysis for the equalizer in the frequency domain. The equalizer implementation is based on an iterative algorithm that contains multiple FFT and IFFT blocks. In addition, multiple mathematical operations are needed in different number domains: real, floating-point and fixed-point. As a result, errors are naturally generated during data conversion between these domains,

Error estimation in Simulink

Error estimation is conducted for the Fast LMS algorithm using simulation in the Simulink environment. The simulation is based on error estimation for the 4-tap frequency domain equalizer, which converges after almost 200 symbols to reach the value of −40 dB. On the other hand, an FPGA based implementation is simulated for a 2-tap equalizer on the one million gate Spartan 3 FPGA board. The results obtained from the Simulink model were better than those obtained from the System Generator model

Formal error analysis

Higher-order-logic (HOL) theorem proving [25] is a formal method that is used to conduct precise analysis of various systems. It is based on a system of deduction with precise semantics and is expressive enough to be used for the precise specification of systems such as the frequency domain equalizer. The HOL theorem prover framework [6] is an interactive tool dedicated to conduct proofs in higher-order logic. There are only four types of terms in HOL: variables, constants, function application

Error estimation in system generator

In order to provide an implementation for the equalizer, we first build a System Generator design implementation model in the frequency domain for the Fast LMS algorithm. This design implementation is obtained using fixed-point arithmetics. The system generator is used to provide a DSP implementation in order to estimate the SNR for the design in the frequency domains, where the error was estimated based on the fixed-point arithmetic model. Hence, the SNR error estimation is obtained for the

Conclusion and future work

In this work, we proposed a design and verification methodology for a frequency domain equalizer implemented using the Fast LMS algorithm in the frequency domain where a number of mathematical operations are performed on numbers in three different domains: floating-point, fixed-point and real numbers. As a result, errors are naturally generated during data conversions between these domains, and can accumulate while performing various algorithmic iterations, such as FFT and IFFT operations. The

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