Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing
Introduction
CMOS technology is reaching its limit beyond which further downscaling in feature size is impossible. High leakage current, high power density levels and high lithography cost crop up with further dimension scaling. One of the emerging nanotechnologies, the Quantum-dot Cellular Automata (QCA), is considered as a viable alternative to meet the energy efficient design target beyond the limit of existing CMOS technology [1], [2]. The major advantages such as low power consumption, zero power dissipation in signal propagation, high speed and high compaction density of QCA based design have attracted researchers to investigate its visibility and implementation constraints.
In VLSI circuits, parity checking techniques reduce the complexity of testing. The parity preserving logic gate, for which the parity of outputs matches with that of the inputs, when used with an arbitrary synthesis strategy for logic circuits, ensures detection of a fault at the primary outputs [3]. The testability feature provided by the existing parity preserving designs often takes the center stage, and the logical depth of a gate is ignored. Further, for testing such logic gate, an additional test logic circuit is considered without utilizing self testable feature.
In QCA paradigm, wire-crossings are a major overhead [4], [5]. Gates that are highly programmable ensure that the larger circuits can be synthesized with fewer number of gates, and thus also reduce the number of wire-crossings. Since majority gate (QCA primitive) itself is not functionally complete, various QCA logic gates such as majority with inverter (MI), CMVMIN (coupled majority minority) [6], UQCLG (universal QCA) [7], NNI (nand-nor-inverter) [8], and AOI (and-or-inverter) [9] are conventionally used for realizing different QCA designs. The design and the fault tolerant capability of CMVMIN gate, reported in [10], [11], are found to be acceptable. However, these gates do not have inherent fault detection or testing features.
All these above factors motivate us to design a new logic gate that can find a trade off between the QCA design costs for test logic and programmability of primary outputs. Also, to continue with the present days' VLSI progress, we move forward for emerging nanotechnology which is desirable to overcome the challenges of feature size reduction and reliability. The major contribution of this work, around parity preserving QCA architecture, can be summarized as follows:
- (i)
This work introduces a design methodology/framework in Quantum-dot cellular automata based on parity preserving logic. A new universal testable QCA logic gate termed as testable-QCA (t-QCA) is proposed. It is a 3×3 gate that realizes minority (min), majority (maj) and XNOR logic at its three primary outputs.
- (ii)
The flexibility of this multi-purpose logic gate enables synthesis of different logic circuits such as benchmark functions as well as arithmetic logic unit. Experimental results establish the effectiveness of the proposed logic and it outperforms the existing technologies in terms of design cost as well as testing overhead.
- (iii)
Reliability issue in nano-circuit, the utmost necessity to overcome the high error rate, is addressed with the achievement of 100% fault coverage.
- (iv)
The parity preserving property enables a t-QCA for concurrent detection of permanent and transient faults by comparing the parity of its inputs and outputs. A simple augmented testing circuit is also proposed, using QCA primitives, that functions as the cost effective comparator.
- (v)
Finally, the flexibility and testability of parity preserving logic are revisited for nano-circuits.
Section snippets
Preliminaries
In QCA based design, a single device (QCA-cell) is used for construction of all the components of a circuit (computational elements and wires). The schematic diagram of a four-dot QCA cell is shown in Fig. 1(a). It contains four quantum dots positioned at the corners of a square and two free electron [2]. A quantum dot is a region where an electron is quantum-mechanically confined (Fig. 1(a)). The coulombic repulsion causes the classical model of electrons to occupy only the four corners of QCA
Related work
Ensuring reliability of devices via parity checking is very much desirable due to its low overhead for storage as well as interconnect. In [13], a novel fault tolerant architecture of majority logic around QCA is proposed. It is effective for high performance logic component design. Design capability/flexibility of QCA design structure is further extended by proposing a 5-input majority gate in [14]. Recently, a QCA circuit with high capability of reconfigurability is presented in [15] to
Universal testable QCA (t-QCA) logic gate
Coupling majority and minority (CMVMIN) function together enables area saving implementation of complex logic [10]. Fault tolerant capability of CMVMIN architecture is also investigated in [11]. In this section, we explore the parity preserving logic in the majority–minority architecture and introduce the self testable logic gate (named t-QCA). The input-to-output mapping of t-QCA is: P=AB+BC+CA, , , where A, B, C are inputs and P, Q, R are the outputs (Fig. 3). The
Logic synthesis with t-QCA
Evaluation of the performance of a logic device also includes the analysis of programmability, that is, the number of logical calculations that can be produced as primary outputs. Although the main objective of this work is to develop a logic device with better testability, we simultaneously try to ensure realization of maximum number of logical functions around it. The proposed t-QCA can be utilized as a programmable logic gate with one select input (C). It then realizes six logical functions
Testing and fault coverage
High fault coverage of a design is desirable during manufacturing test. The techniques such as design for test (DFT) and automatic test pattern generation target to improve the fault efficiency/coverage of a logic design.
Conclusion
This paper proposes a QCA logic gate (t-QCA) based on parity preserving logic that is highly programmable (66.66% improvement) as well as testable. The t-QCA gate outperforms the most popular logic gates in terms of high level logic synthesis and fault coverage. The number of test vectors to detect all possible stuck-at-faults (only four vectors) as well as single missing/additional cell defects (only two test vectors, all 0 s and all 1 s) for coplanar t-QCA is reduced. For single missing cell
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